/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/smumgr/ |
H A D | vega10_smumgr.h | 46 bool enable, uint32_t feature_mask);
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H A D | vega12_smumgr.h | 52 bool enable, uint64_t feature_mask);
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H A D | vega20_smumgr.h | 51 bool enable, uint64_t feature_mask);
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H A D | vega12_smumgr.c | 126 bool enable, uint64_t feature_mask) 130 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); 131 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); 125 vega12_enable_smc_features(struct pp_hwmgr *hwmgr, bool enable, uint64_t feature_mask) argument
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H A D | vega20_smumgr.c | 318 bool enable, uint64_t feature_mask) 323 smu_features_low = (uint32_t)((feature_mask & SMU_FEATURES_LOW_MASK) >> SMU_FEATURES_LOW_SHIFT); 324 smu_features_high = (uint32_t)((feature_mask & SMU_FEATURES_HIGH_MASK) >> SMU_FEATURES_HIGH_SHIFT); 317 vega20_enable_smc_features(struct pp_hwmgr *hwmgr, bool enable, uint64_t feature_mask) argument
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H A D | vega10_smumgr.c | 112 bool enable, uint32_t feature_mask) 126 msg, feature_mask, NULL); 111 vega10_enable_smc_features(struct pp_hwmgr *hwmgr, bool enable, uint32_t feature_mask) argument
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H A D | smu7_smumgr.c | 578 (hwmgr->feature_mask & PP_AVFS_MASK))
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/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
H A D | hwmgr.c | 102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | 113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; 118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; 123 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | 131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; 136 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | 144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); 149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); 160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; 170 hwmgr->feature_mask [all...] |
H A D | vega20_hwmgr.c | 103 if (!(hwmgr->feature_mask & PP_PCIE_DPM_MASK)) 106 if (!(hwmgr->feature_mask & PP_SCLK_DPM_MASK)) 109 if (!(hwmgr->feature_mask & PP_SOCCLK_DPM_MASK)) 112 if (!(hwmgr->feature_mask & PP_MCLK_DPM_MASK)) 115 if (!(hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK)) 118 if (!(hwmgr->feature_mask & PP_ULV_MASK)) 121 if (!(hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK)) 173 data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK); 1809 static int vega20_upload_dpm_min_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) argument 1817 (feature_mask 1910 vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_mask) argument [all...] |
H A D | vega10_hwmgr.c | 120 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 122 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; 124 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 126 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; 129 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; 131 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { 138 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; 141 hwmgr->feature_mask & PP_ULV_MASK ? true : false; 144 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; 153 hwmgr->feature_mask 2892 uint32_t i, feature_mask = 0; local 2931 uint32_t i, feature_mask = 0; local 5648 uint32_t feature_mask = 0; local [all...] |
H A D | smu7_clockpowergating.c | 175 if (!(hwmgr->feature_mask & PP_ENABLE_GFX_CG_THRU_SMU))
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/ |
H A D | smu_cmn.c | 589 uint64_t *feature_mask) 595 if (!feature_mask) 598 feature_mask_low = &((uint32_t *)feature_mask)[0]; 599 feature_mask_high = &((uint32_t *)feature_mask)[1]; 645 uint64_t feature_mask, 653 lower_32_bits(feature_mask), 659 upper_32_bits(feature_mask), 664 lower_32_bits(feature_mask), 670 upper_32_bits(feature_mask), 712 uint64_t feature_mask; local 588 smu_cmn_get_enabled_mask(struct smu_context *smu, uint64_t *feature_mask) argument 644 smu_cmn_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled) argument 757 uint64_t feature_mask; local [all...] |
H A D | smu_cmn.h | 75 uint64_t *feature_mask); 82 uint64_t feature_mask,
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H A D | smu_internal.h | 75 #define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num)
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/ |
H A D | smu_v13_0_7_ppt.c | 258 uint32_t *feature_mask, uint32_t num) 265 memset(feature_mask, 0, sizeof(uint32_t) * num); 267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); 270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); 272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); 276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); 281 *(uint64_t *)feature_mask | 257 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) argument [all...] |
H A D | smu_v13_0_0_ppt.c | 289 uint32_t *feature_mask, uint32_t num) 297 memset(feature_mask, 0xff, sizeof(uint32_t) * num); 300 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 301 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT); 306 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT); 309 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT); 315 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT); 318 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT); 319 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT); 320 *(uint64_t *)feature_mask 288 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) argument [all...] |
H A D | aldebaran_ppt.c | 298 uint32_t *feature_mask, uint32_t num) 304 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 938 uint32_t feature_mask, 947 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) { 961 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) { 975 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) { 1670 uint32_t feature_mask; member in struct:throttling_logging_label 1696 if (throttler_status & logging_label[throttler_idx].feature_mask) { 297 aldebaran_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) argument 936 aldebaran_upload_dpm_level(struct smu_context *smu, bool max, uint32_t feature_mask, uint32_t level) argument
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H A D | smu_v13_0_6_ppt.c | 287 uint32_t *feature_mask, 294 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 1007 uint32_t feature_mask, uint32_t level) 1014 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) { 1030 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) { 1047 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) { 1645 uint64_t *feature_mask) 1651 ret = smu_cmn_get_enabled_mask(smu, feature_mask); 1654 *feature_mask = 0; 286 smu_v13_0_6_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) argument 1006 smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max, uint32_t feature_mask, uint32_t level) argument 1644 smu_v13_0_6_get_enabled_mask(struct smu_context *smu, uint64_t *feature_mask) argument
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu11/ |
H A D | cyan_skillfish_ppt.c | 566 uint64_t *feature_mask) 568 if (!feature_mask) 570 memset(feature_mask, 0xff, sizeof(*feature_mask)); 565 cyan_skillfish_get_enabled_mask(struct smu_context *smu, uint64_t *feature_mask) argument
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H A D | navi10_ppt.c | 279 uint32_t *feature_mask, uint32_t num) 286 memset(feature_mask, 0, sizeof(uint32_t) * num); 288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); 323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); 326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); 329 *(uint64_t *)feature_mask | 278 navi10_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) argument [all...] |
H A D | arcturus_ppt.c | 316 uint32_t *feature_mask, uint32_t num) 322 memset(feature_mask, 0xFF, sizeof(uint32_t) * num); 949 uint32_t feature_mask, 958 (feature_mask & FEATURE_DPM_GFXCLK_MASK)) { 972 (feature_mask & FEATURE_DPM_UCLK_MASK)) { 986 (feature_mask & FEATURE_DPM_SOCCLK_MASK)) { 2304 uint32_t feature_mask; member in struct:throttling_logging_label 2332 if (throttler_status & logging_label[throttler_idx].feature_mask) { 315 arcturus_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) argument 947 arcturus_upload_dpm_level(struct smu_context *smu, bool max, uint32_t feature_mask, uint32_t level) argument
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H A D | sienna_cichlid_ppt.c | 276 uint32_t *feature_mask, uint32_t num) 283 memset(feature_mask, 0, sizeof(uint32_t) * num); 285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) 307 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); 308 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT); 314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT); 317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) 322 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); 325 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); 328 *(uint64_t *)feature_mask | 275 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) argument [all...] |
H A D | smu_v11_0.c | 751 uint32_t feature_mask[2]; local 758 bitmap_to_arr32(feature_mask, feature->allowed, 64); 761 feature_mask[1], NULL); 766 feature_mask[0], NULL);
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu12/ |
H A D | renoir_ppt.c | 1414 uint64_t *feature_mask) 1416 if (!feature_mask) 1418 memset(feature_mask, 0xff, sizeof(*feature_mask)); 1413 renoir_get_enabled_mask(struct smu_context *smu, uint64_t *feature_mask) argument
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/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/ |
H A D | amdgpu_smu.h | 583 * &feature_mask: Array to store feature mask. 584 * &num: Elements in &feature_mask. 586 int (*get_allowed_feature_mask)(struct smu_context *smu, uint32_t *feature_mask, uint32_t num); 1015 * &feature_mask: Enabled feature mask. 1017 int (*get_enabled_mask)(struct smu_context *smu, uint64_t *feature_mask);
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