powerplay/hwmgr/vega10_hwmgr.c

120 			hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
122 			hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true;
124 			hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
126 			hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true;
129 			hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true;
131 	if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) {
138 			hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false;
141 			hwmgr->feature_mask & PP_ULV_MASK ? true : false;
144 			hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false;
153 		hwmgr->feature_mask & PP_AVFS_MASK ? true : false;
2892 	uint32_t i, feature_mask = 0;
2908 					feature_mask |= data->smu_features[i].
2916 	vega10_enable_smc_features(hwmgr, false, feature_mask);
2931 	uint32_t i, feature_mask = 0;
2937 					feature_mask |= data->smu_features[i].
2946 			true, feature_mask)) {
2949 					feature_mask)
5648 	uint32_t feature_mask = 0;
5651 		feature_mask |= data->smu_features[GNLD_ULV].enabled ?
5653 		feature_mask |= data->smu_features[GNLD_DS_GFXCLK].enabled ?
5655 		feature_mask |= data->smu_features[GNLD_DS_SOCCLK].enabled ?
5657 		feature_mask |= data->smu_features[GNLD_DS_LCLK].enabled ?
5659 		feature_mask |= data->smu_features[GNLD_DS_DCEFCLK].enabled ?
5662 		feature_mask |= (!data->smu_features[GNLD_ULV].enabled) ?
5664 		feature_mask |= (!data->smu_features[GNLD_DS_GFXCLK].enabled) ?
5666 		feature_mask |= (!data->smu_features[GNLD_DS_SOCCLK].enabled) ?
5668 		feature_mask |= (!data->smu_features[GNLD_DS_LCLK].enabled) ?
5670 		feature_mask |= (!data->smu_features[GNLD_DS_DCEFCLK].enabled) ?
5674 	if (feature_mask)
5676 				!disable, feature_mask),