Searched refs:dram_speed_mts (Results 1 - 16 of 16) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c118 .dram_speed_mts = 16000.0,
168 entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans *
174 entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans *
176 } else if (entry->dram_speed_mts > 0) {
177 float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans *
192 memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans *
301 if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
437 entry.dram_speed_mts = 0;
447 entry.dram_speed_mts
699 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; local
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c197 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; local
279 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
283 dram_speed_mts[num_states++] =
293 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
299 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
307 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
330 if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700)
333 if (dcn3_03_soc.clock_limits[i].dram_speed_mts >= 1500) {
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.h64 unsigned int *dram_speed_mts);
H A Ddcn30_fpu.c500 dc->clk_mgr->bw_params->dummy_pstate_table[dummy_latency_index].dram_speed_mts)
575 if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) {
576 context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts;
643 unsigned int *dram_speed_mts)
656 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
770 base->bw_params->dummy_pstate_table[0].dram_speed_mts = 1600;
772 base->bw_params->dummy_pstate_table[1].dram_speed_mts = 8000;
774 base->bw_params->dummy_pstate_table[2].dram_speed_mts = 10000;
776 base->bw_params->dummy_pstate_table[3].dram_speed_mts
639 dcn30_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params, struct dc_bounding_box_max_clk *dcn30_bb_max_clk, unsigned int *dcfclk_mhz, unsigned int *dram_speed_mts) argument
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c201 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; local
285 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
289 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
298 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
304 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
312 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c116 .dram_speed_mts = 2400.0,
128 .dram_speed_mts = 2400.0,
140 .dram_speed_mts = 4267.0,
152 .dram_speed_mts = 4267.0,
164 .dram_speed_mts = 4267.0,
354 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
394 ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
395 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_socbb.h31 uint32_t dram_speed_mts; member in struct:gpu_info_voltage_scaling_v1_0
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c230 .dram_speed_mts = 8960.0,
241 .dram_speed_mts = 11104.0,
252 .dram_speed_mts = 14000.0,
263 .dram_speed_mts = 16000.0,
274 .dram_speed_mts = 16000.0,
286 .dram_speed_mts = 16000.0,
341 .dram_speed_mts = 8960.0,
352 .dram_speed_mts = 11104.0,
363 .dram_speed_mts = 14000.0,
374 .dram_speed_mts
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c129 .dram_speed_mts = 18000.0,
233 clk_mgr->base.bw_params->dummy_pstate_table[0].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz * 16;
235 clk_mgr->base.bw_params->dummy_pstate_table[1].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[1].memclk_mhz * 16;
237 clk_mgr->base.bw_params->dummy_pstate_table[2].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz * 16;
239 clk_mgr->base.bw_params->dummy_pstate_table[3].dram_speed_mts = clk_mgr->base.bw_params->clk_table.entries[3].memclk_mhz * 16;
441 memory_bw_kbytes_sec = entry->dram_speed_mts *
471 entry->dram_speed_mts = bw_on_sdp / (dcn3_2_soc.num_chans *
477 entry->dram_speed_mts = bw_on_fabric / (dcn3_2_soc.num_chans *
479 } else if (entry->dram_speed_mts > 0) {
480 float bw_on_dram = entry->dram_speed_mts * dcn3_2_so
2788 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; local
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h223 unsigned int dram_speed_mts; member in struct:dummy_pstate_entry
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_resource.c150 .dram_speed_mts = 2000.0,
161 .dram_speed_mts = 3600.0,
172 .dram_speed_mts = 6800.0,
183 .dram_speed_mts = 14000.0,
194 .dram_speed_mts = 14000.0,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h163 double dram_speed_mts; member in struct:_vcs_dpi_voltage_scaling_st
H A Ddisplay_mode_vba.c382 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts;
403 mode_lib->vba.DRAMSpeedPerState[i] = soc->clock_limits[i].dram_speed_mts;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c624 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz *
692 dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
776 s[i].dram_speed_mts = clk_table->entries[i].memclk_mhz *
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2095 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0}; local
2177 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2181 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2190 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2196 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2201 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mts);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c241 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;

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