dml/dcn321/dcn321_fpu.c

118 			.dram_speed_mts = 16000.0,
168 		entry->dram_speed_mts = bw_on_sdp / (dcn3_21_soc.num_chans *
174 		entry->dram_speed_mts = bw_on_fabric / (dcn3_21_soc.num_chans *
176 	} else if (entry->dram_speed_mts > 0) {
177 		float bw_on_dram = entry->dram_speed_mts * dcn3_21_soc.num_chans *
192 	memory_bw_kbytes_sec = entry->dram_speed_mts * dcn3_21_soc.num_chans *
301 			if ((table[i].dram_speed_mts > table[i+1].dram_speed_mts) ||
437 		entry.dram_speed_mts = 0;
447 	entry.dram_speed_mts = 0;
457 		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;
469 			entry.dram_speed_mts = 0;
480 		entry.dram_speed_mts = 0;
495 				table[i].dram_speed_mts > max_clk_data.memclk_mhz * 16)
505 		max_dc_limits_entry.dram_speed_mts = max_clk_data.memclk_mhz * 16;
524 			if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {
525 				table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;
563 				table[i].dram_speed_mts == table[i + 1].dram_speed_mts)
699 		unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
770 				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
774 					dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
783 			dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
789 			dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
820 			if (!dram_speed_mts[i] && i > 0)
821 				dcn3_21_soc.clock_limits[i].dram_speed_mts = dcn3_21_soc.clock_limits[i-1].dram_speed_mts;
823 				dcn3_21_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];