Searched refs:dcfclk_sta_targets (Results 1 - 5 of 5) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c205 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; local
242 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
244 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
246 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
249 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
250 dcfclk_sta_targets[i] = max_dcfclk_mhz;
271 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
283 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c201 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; local
238 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
239 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
241 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
243 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
244 dcfclk_sta_targets[i] = max_dcfclk_mhz;
265 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
277 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c354 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; local
435 entry.dcfclk_mhz = dcfclk_sta_targets[i];
703 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {615, 906, 1324, 1564}; local
726 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
728 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
730 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
733 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
734 dcfclk_sta_targets[i] = max_dcfclk_mhz;
756 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
768 if (dcfclk_sta_targets[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2099 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200}; local
2131 if (dcn30_bb_max_clk.max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2133 dcfclk_sta_targets[num_dcfclk_sta_targets] = dcn30_bb_max_clk.max_dcfclk_mhz;
2135 } else if (dcn30_bb_max_clk.max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2138 if (dcfclk_sta_targets[i] > dcn30_bb_max_clk.max_dcfclk_mhz) {
2139 dcfclk_sta_targets[i] = dcn30_bb_max_clk.max_dcfclk_mhz;
2163 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2175 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2176 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2189 dcfclk_mhz[num_states] = dcfclk_sta_targets[
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c2458 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; local
2539 entry.dcfclk_mhz = dcfclk_sta_targets[i];
2794 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564}; local
2811 if (min_dcfclk > dcfclk_sta_targets[0])
2812 dcfclk_sta_targets[0] = min_dcfclk;
2822 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2824 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2826 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2829 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2830 dcfclk_sta_targets[
[all...]

Completed in 202 milliseconds