Lines Matching refs:dcfclk_sta_targets
2458 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2539 entry.dcfclk_mhz = dcfclk_sta_targets[i];
2794 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};
2811 if (min_dcfclk > dcfclk_sta_targets[0])
2812 dcfclk_sta_targets[0] = min_dcfclk;
2822 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2824 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2826 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2829 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2830 dcfclk_sta_targets[i] = max_dcfclk_mhz;
2852 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2864 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2865 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2878 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];