Searched refs:UVD_CGC_CTRL (Results 1 - 8 of 8) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Duvd_v5_0.c688 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
689 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
H A Duvd_v6_0.c1345 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1346 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
H A Duvd_v7_0.c1629 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1630 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
H A Dsid.h1630 #define UVD_CGC_CTRL 0x3dc2 macro
/openbsd-current/sys/dev/pci/drm/radeon/
H A Dsi.c5175 tmp = RREG32(UVD_CGC_CTRL);
5187 WREG32(UVD_CGC_CTRL, tmp);
5198 u32 tmp = RREG32(UVD_CGC_CTRL);
5200 WREG32(UVD_CGC_CTRL, tmp);
5460 orig = data = RREG32(UVD_CGC_CTRL);
5463 WREG32(UVD_CGC_CTRL, data);
5472 orig = data = RREG32(UVD_CGC_CTRL);
5475 WREG32(UVD_CGC_CTRL, data);
H A Dcikd.h2085 #define UVD_CGC_CTRL 0xF4B0 macro
H A Dsid.h1568 #define UVD_CGC_CTRL 0xF4B0 macro
H A Dcik.c6212 orig = data = RREG32(UVD_CGC_CTRL);
6215 WREG32(UVD_CGC_CTRL, data);
6221 orig = data = RREG32(UVD_CGC_CTRL);
6224 WREG32(UVD_CGC_CTRL, data);

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