Searched refs:SU (Results 1 - 25 of 80) sorted by relevance

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/openbsd-current/gnu/llvm/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.h72 inline unsigned getNumDecoderSlots(SUnit *SU) const;
75 bool fitsIntoCurrentGroup(SUnit *SU) const;
82 /// representing the current decoder slot of the current cycle. If an SU
85 unsigned getCurrCycleIdx(SUnit *SU = nullptr) const;
104 bool isFPdOpPreferred_distance(SUnit *SU) const;
116 HazardType getHazardType(SUnit *SU, int Stalls = 0) override;
118 void EmitInstruction(SUnit *SU) override;
121 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
122 if (!SU->SchedClass && SchedModel->hasInstrSchedModel())
123 SU
[all...]
H A DSystemZHazardRecognizer.cpp46 getNumDecoderSlots(SUnit *SU) const {
47 const MCSchedClassDesc *SC = getSchedClass(SU);
61 unsigned SystemZHazardRecognizer::getCurrCycleIdx(SUnit *SU) const {
66 if (SU != nullptr && !fitsIntoCurrentGroup(SU)) {
77 getHazardType(SUnit *SU, int Stalls) { argument
78 return (fitsIntoCurrentGroup(SU) ? NoHazard : Hazard);
92 SystemZHazardRecognizer::fitsIntoCurrentGroup(SUnit *SU) const {
93 const MCSchedClassDesc *SC = getSchedClass(SU);
105 if (CurrGroupSize == 2 && has4RegOps(SU
167 dumpSU(SUnit *SU, raw_ostream &OS) const argument
271 EmitInstruction(SUnit *SU) argument
387 resourcesCost(SUnit *SU) argument
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H A DSystemZMachineScheduler.cpp29 for (auto &SU : *this) {
30 HazardRec.dumpSU(SU, dbgs());
31 if (SU != *rbegin())
176 for (auto *SU : Available) {
178 // SU is the next candidate to be compared against current Best.
179 Candidate c(SU, *HazardRec);
181 // Remeber which SU is the best candidate.
182 if (Best.SU == nullptr || c < Best) {
187 LLVM_DEBUG(HazardRec->dumpSU(c.SU, dbgs()); c.dumpCosts();
188 dbgs() << " Height:" << c.SU
241 schedNode(SUnit *SU, bool IsTopNode) argument
251 releaseTopNode(SUnit *SU) argument
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/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DGCNMinRegStrategy.cpp25 const SUnit *SU; member in struct:__anon2631::GCNMinRegScheduler::Candidate
29 : SU(SU_), Priority(Priority_) {}
38 bool isScheduled(const SUnit *SU) const {
39 assert(!SU->isBoundaryNode());
40 return NumPreds[SU->NodeNum] == std::numeric_limits<unsigned>::max();
43 void setIsScheduled(const SUnit *SU) { argument
44 assert(!SU->isBoundaryNode());
45 NumPreds[SU->NodeNum] = std::numeric_limits<unsigned>::max();
48 unsigned getNumPreds(const SUnit *SU) const {
49 assert(!SU
54 decNumPreds(const SUnit *SU) argument
193 auto SU = Worklist.pop_back_val(); local
213 releaseSuccessors(const SUnit* SU, int Priority) argument
252 auto SU = C->SU; local
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H A DGCNILPSched.cpp23 SUnit *SU; member in struct:__anon2629::GCNILPScheduler::Candidate
26 : SU(SU_) {}
40 unsigned getNodePriority(const SUnit *SU) const;
47 void releasePredecessors(const SUnit* SU);
58 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { argument
59 unsigned &SethiUllmanNumber = SUNumbers[SU->NodeNum];
64 for (const SDep &Pred : SU->Preds) {
86 unsigned GCNILPScheduler::getNodePriority(const SUnit *SU) const {
87 assert(SU->NodeNum < SUNumbers.size());
88 if (SU
106 closestSucc(const SUnit *SU) argument
121 calcMaxScratches(const SUnit *SU) argument
275 releasePredecessors(const SUnit* SU) argument
336 auto SU = C->SU; local
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H A DAMDGPUExportClustering.cpp29 static bool isExport(const SUnit &SU) { argument
30 return SIInstrInfo::isEXP(*SU.getInstr());
33 static bool isPositionExport(const SIInstrInfo *TII, SUnit *SU) { argument
34 const MachineInstr *MI = SU->getInstr();
51 for (SUnit *SU : Copy) {
52 if (isPositionExport(TII, SU))
53 Chain[PosIdx++] = SU;
55 Chain[OtherIdx++] = SU;
82 static void removeExportDependencies(ScheduleDAGInstrs *DAG, SUnit &SU) { argument
85 for (const SDep &Pred : SU
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H A DR600MachineScheduler.cpp53 SUnit *SU = nullptr; local
93 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
96 SU = pickAlu();
97 if (!SU && !PhysicalRegCopy.empty()) {
98 SU = PhysicalRegCopy.front();
101 if (SU) {
108 if (!SU) {
110 SU = pickOther(IDFetch);
111 if (SU)
116 if (!SU) {
135 schedNode(SUnit *SU, bool IsTopNode) argument
182 releaseTopNode(SUnit *SU) argument
186 releaseBottomNode(SUnit *SU) argument
286 getInstKind(SUnit* SU) argument
315 SUnit *SU = *It; local
424 SUnit *SU = AttemptFillSlot(3, true); local
433 SUnit *SU = AttemptFillSlot(Chan, false); local
447 SUnit *SU = nullptr; local
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H A DSIMachineScheduler.cpp178 void SIScheduleBlock::addUnit(SUnit *SU) { argument
179 NodeNum2Index[SU->NodeNum] = SUnits.size();
180 SUnits.push_back(SU);
186 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
238 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
246 for (SUnit* SU : TopReadySUs) {
251 TryCand.SU = SU;
280 SUnit *SU = TopReadySUs[0]; local
398 SUnit *SU = pickNode(); local
434 undoReleaseSucc(SUnit *SU, SDep *SuccEdge) argument
444 releaseSucc(SUnit *SU, SDep *SuccEdge) argument
464 releaseSuccessors(SUnit *SU, bool InOrOutBlock) argument
480 nodeScheduled(SUnit *SU) argument
627 isSUInBlock(SUnit *SU, unsigned ID) argument
637 SUnit *SU = &DAG->SUnits[i]; local
645 hasDataDependencyPred(const SUnit &SU, const SUnit &FromSU) argument
663 SUnit *SU = &DAG->SUnits[i]; local
679 const SUnit &SU = DAG->SUnits[SUNum]; local
791 SUnit *SU = &DAG->SUnits[SUNum]; local
833 SUnit *SU = &DAG->SUnits[SUNum]; local
914 SUnit *SU = &DAG->SUnits[SUNum]; local
958 SUnit *SU = &DAG->SUnits[i]; local
984 SUnit *SU = &DAG->SUnits[SUNum]; local
1010 SUnit *SU = &DAG->SUnits[SUNum]; local
1031 SUnit *SU = &DAG->SUnits[SUNum]; local
1053 SUnit *SU = &DAG->SUnits[SUNum]; local
1059 SUnit *SU = &DAG->SUnits[SUNum]; local
1092 SUnit *SU = &DAG->SUnits[SUNum]; local
1124 const SUnit &SU = DAG->SUnits[SUNum]; local
1189 SUnit *SU = &DAG->SUnits[i]; local
1203 SUnit *SU = &DAG->SUnits[i]; local
1787 SUnit *SU = &SUnits[ScheduledSUnits[i]]; local
1915 SUnit *SU = &SUnits[i]; local
1990 SUnit *SU = &SUnits[I]; local
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/openbsd-current/gnu/llvm/llvm/lib/CodeGen/
H A DLatencyPriorityQueue.cpp55 /// of SU, return it, otherwise return null.
56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument
58 for (const SDep &P : SU->Preds) {
72 void LatencyPriorityQueue::push(SUnit *SU) { argument
76 for (const SDep &Succ : SU->Succs)
77 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU)
79 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
81 Queue.push_back(SU);
89 void LatencyPriorityQueue::scheduledNode(SUnit *SU) { argument
90 for (const SDep &Succ : SU
100 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument
129 remove(SUnit *SU) argument
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H A DVLIWMachineScheduler.cpp103 /// Check if scheduling of this SU is possible
108 bool VLIWResourceModel::isResourceAvailable(SUnit *SU, bool IsTop) { argument
109 if (!SU || !SU->getInstr())
114 switch (SU->getInstr()->getOpcode()) {
116 if (!ResourcesModel->canReserveResources(*SU->getInstr()))
134 if (hasDependence(Packet[i], SU))
138 if (hasDependence(SU, Packet[i]))
145 bool VLIWResourceModel::reserveResources(SUnit *SU, bool IsTop) { argument
148 if (!SU) {
244 SUnit *SU = SchedImpl->pickNode(IsTopNode); local
310 releaseTopNode(SUnit *SU) argument
325 releaseBottomNode(SUnit *SU) argument
361 checkHazard(SUnit *SU) argument
372 releaseNode( SUnit *SU, unsigned ReadyCycle) argument
414 bumpNode(SUnit *SU) argument
451 SUnit *SU = *(Pending.begin() + i); local
472 removeReady(SUnit *SU) argument
510 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, int Cost, PressureChange P) argument
548 isSingleUnscheduledPred(SUnit *SU, SUnit *SU2) argument
563 isSingleUnscheduledSucc(SUnit *SU, SUnit *SU2) argument
580 pressureChange(const SUnit *SU, bool isBotUp) argument
596 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument
956 SUnit *SU; local
999 schedNode(SUnit *SU, bool IsTopNode) argument
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H A DScheduleDAGInstrs.cpp104 for (const SUnit *SU : L) {
105 dbgs() << "SU(" << SU->NodeNum << ")";
106 if (SU != L.back())
233 /// MO is an operand of SU's instruction that defines a physical register. Adds
234 /// data dependencies from SU to any uses of the physical register.
235 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument
236 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
244 const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
250 SUnit *UseSU = I->SU;
288 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument
392 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument
511 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument
574 SUnit *SU = newSUnit(&MI); local
628 insert(SUnit *SU, ValueType V) argument
666 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap) argument
673 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) argument
814 SUnit *SU = MISUnitMap[&MI]; local
1266 visitPreorder(const SUnit *SU) argument
1274 visitPostorderNode(const SUnit *SU) argument
1423 follow(const SUnit *SU) argument
1444 hasDataSucc(const SUnit *SU) argument
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H A DMultiHazardRecognizer.cpp34 MultiHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument
36 auto res = R->getHazardType(SU, Stalls);
48 void MultiHazardRecognizer::EmitInstruction(SUnit *SU) { argument
50 R->EmitInstruction(SU);
58 unsigned MultiHazardRecognizer::PreEmitNoops(SUnit *SU) { argument
60 return std::max(a, R->PreEmitNoops(SU));
72 bool MultiHazardRecognizer::ShouldPreferAnother(SUnit *SU) { argument
74 return R->ShouldPreferAnother(SU);
/openbsd-current/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp67 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument
69 for (SDep &Pred : SU->Preds) {
104 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument
107 for (const SDep &Succ : SU->Succs) {
142 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument
144 for (const SDep &Succ : SU->Succs)
151 static unsigned numberCtrlPredInSU(SUnit *SU) { argument
153 for (SDep &Pred : SU->Preds)
167 for (SUnit &SU : *SUnits) {
168 initNumRegDefsLeft(&SU);
209 getSingleUnscheduledPred(SUnit *SU) argument
224 push(SUnit *SU) argument
238 isResourceAvailable(SUnit *SU) argument
281 reserveResources(SUnit *SU) argument
318 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument
352 regPressureDelta(SUnit *SU, bool RawPressure) argument
388 SUSchedulingCost(SUnit *SU) argument
459 scheduledNode(SUnit *SU) argument
533 initNumRegDefsLeft(SUnit *SU) argument
566 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument
617 remove(SUnit *SU) argument
[all...]
H A DScheduleDAGVLIW.cpp81 void releaseSucc(SUnit *SU, const SDep &D);
82 void releaseSuccessors(SUnit *SU);
83 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
109 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument
124 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
133 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument
135 for (SDep &Succ : SU->Succs) {
139 releaseSucc(SU, Succ);
146 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { argument
148 LLVM_DEBUG(dumpNode(*SU));
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H A DScheduleDAGRRList.cpp211 /// IsReachable - Checks if SU is reachable from TargetSU.
212 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument
213 return Topo.IsReachable(SU, TargetSU);
216 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
218 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument
219 return Topo.WillCreateCycle(SU, TargetSU);
222 /// AddPredQueued - Queues and update to add a predecessor edge to SUnit SU.
225 void AddPredQueued(SUnit *SU, const SDep &D) { argument
226 Topo.AddPredQueued(SU, D.getSUnit());
227 SU
233 AddPred(SUnit *SU, const SDep &D) argument
241 RemovePred(SUnit *SU, const SDep &D) argument
247 isReady(SUnit *SU) argument
401 ReleasePred(SUnit *SU, const SDep *PredEdge) argument
557 ReleasePredecessors(SUnit *SU) argument
654 AdvancePastStalls(SUnit *SU) argument
696 EmitNode(SUnit *SU) argument
739 ScheduleNodeBottomUp(SUnit *SU) argument
838 UnscheduleNodeBottomUp(SUnit *SU) argument
941 SUnit *SU = *I; local
951 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument
973 isOperandOf(const SUnit *SU, SDNode *N) argument
983 TryUnfoldSU(SUnit *SU) argument
1137 CopyAndMoveSuccessors(SUnit *SU) argument
1225 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument
1301 CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI, const SDNode *Node = nullptr) argument
1327 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, ArrayRef<SUnit*> LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument
1354 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument
1452 SUnit *SU = Interferences[i-1]; local
1632 SUnit *SU = PickNodeToScheduleBottomUp(); local
1923 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); variable
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/openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h30 bool isLoadAfterStore(SUnit *SU);
31 bool isBCTRAfterSet(SUnit *SU);
39 HazardType getHazardType(SUnit *SU, int Stalls) override;
40 bool ShouldPreferAnother(SUnit* SU) override;
41 unsigned PreEmitNoops(SUnit *SU) override;
42 void EmitInstruction(SUnit *SU) override;
78 HazardType getHazardType(SUnit *SU, int Stalls) override;
79 void EmitInstruction(SUnit *SU) override;
H A DPPCHazardRecognizers.cpp24 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { argument
26 if (isBCTRAfterSet(SU))
29 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
36 // SU is a load; for any predecessors in this dispatch group, that are stores,
38 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
43 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
47 if (SU->Preds[i].getSUnit() == CurGroup[j])
54 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { argument
139 getHazardType(SUnit *SU, int Stalls) argument
146 ShouldPreferAnother(SUnit *SU) argument
155 PreEmitNoops(SUnit *SU) argument
174 EmitInstruction(SUnit *SU) argument
325 getHazardType(SUnit *SU, int Stalls) argument
385 EmitInstruction(SUnit *SU) argument
[all...]
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI ||
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8;
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) {
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) {
61 if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop),
62 biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg))
92 if (tryLess(Zone->getLatencyStallCycles(TryCand.SU),
93 Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
107 if (tryGreater(TryCand.SU == TryCandNextClusterSU,
108 Cand.SU
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/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp45 int HexagonConvergingVLIWScheduler::SchedulingCost(ReadyQueue &Q, SUnit *SU, argument
50 ConvergingVLIWScheduler::SchedulingCost(Q, SU, Candidate, Delta, verbose);
52 if (!SU || SU->isScheduled)
57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) {
59 Top.ResourceModel->isResourceAvailable(SU, true)) {
63 Bot.ResourceModel->isResourceAvailable(SU, false)) {
H A DHexagonHazardRecognizer.cpp39 HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { argument
40 MachineInstr *MI = SU->getInstr();
63 if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) {
95 bool HexagonHazardRecognizer::ShouldPreferAnother(SUnit *SU) { argument
96 if (PrefVectorStoreNew != nullptr && PrefVectorStoreNew != SU)
98 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad())
100 return UsesDotCur && ((SU == UsesDotCur) ^ (DotCurPNum == (int)PacketNum));
112 void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { argument
113 MachineInstr *MI = SU
[all...]
/openbsd-current/gnu/llvm/llvm/include/llvm/CodeGen/
H A DResourcePriorityQueue.h83 void addNode(const SUnit *SU) override {
87 void updateNode(const SUnit *SU) override {}
103 /// Single cost function reflecting benefit of scheduling SU
105 int SUSchedulingCost (SUnit *SU);
109 void initNumRegDefsLeft(SUnit *SU);
110 int regPressureDelta(SUnit *SU, bool RawPressure = false);
111 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
119 void remove(SUnit *SU) override;
122 void scheduledNode(SUnit *SU) override;
123 bool isResourceAvailable(SUnit *SU);
[all...]
H A DScheduleDAGInstrs.h56 SUnit *SU; member in struct:llvm::VReg2SUnit
58 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) argument
59 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
71 unsigned OperandIndex, SUnit *SU)
72 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
78 SUnit *SU; member in struct:llvm::PhysRegSUOper
82 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
181 /// No other SU ever gets scheduled around it (except in the special
199 /// every Nth memory SU int
70 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU) argument
211 addChainDependencies(SUnit *SU, SUList &SUs, unsigned Latency) argument
273 IsReachable(SUnit *SU, SUnit *TargetSU) argument
[all...]
H A DLatencyPriorityQueue.h57 void addNode(const SUnit *SU) override {
61 void updateNode(const SUnit *SU) override {
84 void remove(SUnit *SU) override;
94 void scheduledNode(SUnit *SU) override;
97 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
98 SUnit *getSingleUnscheduledPred(SUnit *SU);
H A DMachineScheduler.h258 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
262 virtual void releaseTopNode(SUnit *SU) = 0;
266 virtual void releaseBottomNode(SUnit *SU) = 0;
370 void updateQueues(SUnit *SU, bool IsTopNode);
384 void releaseSucc(SUnit *SU, SDep *SuccEdge);
385 void releaseSuccessors(SUnit *SU);
386 void releasePred(SUnit *SU, SDep *PredEdge);
387 void releasePredecessors(SUnit *SU);
406 // Map each SU to its summary of pressure changes. This array is updated for
460 PressureDiff &getPressureDiff(const SUnit *SU) { argument
563 find(SUnit *SU) argument
565 push(SUnit *SU) argument
894 SUnit *SU; member in struct:llvm::GenericSchedulerBase::SchedCandidate
[all...]
H A DVLIWMachineScheduler.h57 virtual bool isResourceAvailable(SUnit *SU, bool IsTop);
58 virtual bool reserveResources(SUnit *SU, bool IsTop);
61 bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); }
94 SUnit *SU = nullptr; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate
175 for (auto &SU : DAG->SUnits)
176 MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth());
185 bool checkHazard(SUnit *SU);
187 void releaseNode(SUnit *SU, unsigne
199 isLatencyBound(SUnit *SU) argument
[all...]

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