Lines Matching refs:SU
178 void SIScheduleBlock::addUnit(SUnit *SU) {
179 NodeNum2Index[SU->NodeNum] = SUnits.size();
180 SUnits.push_back(SU);
186 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
238 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
246 for (SUnit* SU : TopReadySUs) {
251 TryCand.SU = SU;
252 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure);
255 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum];
256 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum];
258 HasLowLatencyNonWaitedParent[NodeNum2Index[SU->NodeNum]];
264 return TopCand.SU;
274 for (SUnit* SU : SUnits) {
275 if (!SU->NumPredsLeft)
276 TopReadySUs.push_back(SU);
280 SUnit *SU = TopReadySUs[0];
281 ScheduledSUnits.push_back(SU);
282 nodeScheduled(SU);
316 // Goes though all SU. RPTracker captures what had to be alive for the SUs
318 for (SUnit* SU : ScheduledSUnits) {
319 RPTracker.setPos(SU->getInstr());
392 for (SUnit* SU : SUnits) {
393 if (!SU->NumPredsLeft)
394 TopReadySUs.push_back(SU);
398 SUnit *SU = pickNode();
399 ScheduledSUnits.push_back(SU);
400 TopRPTracker.setPos(SU->getInstr());
402 nodeScheduled(SU);
412 for (SUnit* SU : SUnits) {
413 assert(SU->isScheduled &&
414 SU->NumPredsLeft == 0);
422 for (SUnit* SU : SUnits) {
423 SU->isScheduled = false;
424 for (SDep& Succ : SU->Succs) {
426 undoReleaseSucc(SU, &Succ);
434 void SIScheduleBlock::undoReleaseSucc(SUnit *SU, SDep *SuccEdge) {
444 void SIScheduleBlock::releaseSucc(SUnit *SU, SDep *SuccEdge) {
463 /// Release Successors of the SU that are in the block or not.
464 void SIScheduleBlock::releaseSuccessors(SUnit *SU, bool InOrOutBlock) {
465 for (SDep& Succ : SU->Succs) {
474 releaseSucc(SU, &Succ);
480 void SIScheduleBlock::nodeScheduled(SUnit *SU) {
482 assert (!SU->NumPredsLeft);
483 std::vector<SUnit *>::iterator I = llvm::find(TopReadySUs, SU);
490 releaseSuccessors(SU, true);
493 if (HasLowLatencyNonWaitedParent[NodeNum2Index[SU->NodeNum]])
496 if (DAG->IsLowLatencySU[SU->NodeNum]) {
497 for (SDep& Succ : SU->Succs) {
504 SU->isScheduled = true;
509 for (SUnit* SU : SUnits) {
510 releaseSuccessors(SU, false);
511 if (DAG->IsHighLatencySU[SU->NodeNum])
595 for (const SUnit* SU : SUnits)
596 DAG->dumpNode(*SU);
627 bool SIScheduleBlockCreator::isSUInBlock(SUnit *SU, unsigned ID) {
628 if (SU->NodeNum >= DAG->SUnits.size())
630 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID;
637 SUnit *SU = &DAG->SUnits[i];
638 if (DAG->IsHighLatencySU[SU->NodeNum]) {
639 CurrentColoring[SU->NodeNum] = NextReservedID++;
645 hasDataDependencyPred(const SUnit &SU, const SUnit &FromSU) {
646 for (const auto &PredDep : SU.Preds) {
663 SUnit *SU = &DAG->SUnits[i];
664 if (DAG->IsHighLatencySU[SU->NodeNum])
679 const SUnit &SU = DAG->SUnits[SUNum];
680 if (DAG->IsHighLatencySU[SU.NodeNum]) {
698 // By construction (topological order), if SU and
700 // in the parent graph of SU.
702 SubGraph = DAG->GetTopo()->GetSubGraph(SU, DAG->SUnits[j],
706 SubGraph = DAG->GetTopo()->GetSubGraph(DAG->SUnits[j], SU,
728 // If one of the SU in the subgraph depends on the result of SU j,
737 // Same check for the SU
738 if (hasDataDependencyPred(SU, DAG->SUnits[j])) {
751 FormingGroup.insert(SU.NodeNum);
754 CurrentColoring[SU.NodeNum] = ProposedColor;
764 FormingGroup.insert(SU.NodeNum);
765 CurrentColoring[SU.NodeNum] = ProposedColor;
791 SUnit *SU = &DAG->SUnits[SUNum];
795 if (CurrentColoring[SU->NodeNum]) {
796 CurrentTopDownReservedDependencyColoring[SU->NodeNum] =
797 CurrentColoring[SU->NodeNum];
801 for (SDep& PredDep : SU->Preds) {
813 CurrentTopDownReservedDependencyColoring[SU->NodeNum] =
819 CurrentTopDownReservedDependencyColoring[SU->NodeNum] = Pos->second;
821 CurrentTopDownReservedDependencyColoring[SU->NodeNum] =
833 SUnit *SU = &DAG->SUnits[SUNum];
837 if (CurrentColoring[SU->NodeNum]) {
838 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] =
839 CurrentColoring[SU->NodeNum];
843 for (SDep& SuccDep : SU->Succs) {
855 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] =
861 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] = Pos->second;
863 CurrentBottomUpReservedDependencyColoring[SU->NodeNum] =
877 for (const SUnit &SU : DAG->SUnits) {
881 if (CurrentColoring[SU.NodeNum])
884 SUColors.first = CurrentTopDownReservedDependencyColoring[SU.NodeNum];
885 SUColors.second = CurrentBottomUpReservedDependencyColoring[SU.NodeNum];
890 CurrentColoring[SU.NodeNum] = Pos->second;
892 CurrentColoring[SU.NodeNum] = NextNonReservedID;
914 SUnit *SU = &DAG->SUnits[SUNum];
918 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
921 if (CurrentBottomUpReservedDependencyColoring[SU->NodeNum] > 0 ||
922 CurrentTopDownReservedDependencyColoring[SU->NodeNum] > 0)
925 for (SDep& SuccDep : SU->Succs) {
938 PendingColoring[SU->NodeNum] = *SUColors.begin();
941 PendingColoring[SU->NodeNum] = NextNonReservedID++;
958 SUnit *SU = &DAG->SUnits[i];
961 assert(i == SU->NodeNum);
967 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
984 SUnit *SU = &DAG->SUnits[SUNum];
987 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
992 if (SU->Preds.size() > 0 && !DAG->IsLowLatencySU[SU->NodeNum])
995 for (SDep& SuccDep : SU->Succs) {
1002 CurrentColoring[SU->NodeNum] = *SUColors.begin();
1010 SUnit *SU = &DAG->SUnits[SUNum];
1013 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1016 for (SDep& SuccDep : SU->Succs) {
1023 CurrentColoring[SU->NodeNum] = *SUColors.begin();
1031 SUnit *SU = &DAG->SUnits[SUNum];
1034 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1037 for (SDep& SuccDep : SU->Succs) {
1044 CurrentColoring[SU->NodeNum] = *SUColors.begin();
1053 SUnit *SU = &DAG->SUnits[SUNum];
1054 unsigned color = CurrentColoring[SU->NodeNum];
1059 SUnit *SU = &DAG->SUnits[SUNum];
1060 unsigned color = CurrentColoring[SU->NodeNum];
1063 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1069 for (SDep& SuccDep : SU->Succs) {
1077 CurrentColoring[SU->NodeNum] = *SUColors.begin();
1092 SUnit *SU = &DAG->SUnits[SUNum];
1095 if (CurrentColoring[SU->NodeNum] <= (int)DAGSize)
1098 for (SDep& SuccDep : SU->Succs) {
1105 CurrentColoring[SU->NodeNum] = GroupID;
1124 const SUnit &SU = DAG->SUnits[SUNum];
1125 if (SIInstrInfo::isEXP(*SU.getInstr())) {
1126 // SU is an export instruction. Check whether one of its successor
1128 for (const SDep &SuccDep : SU.Succs) {
1189 SUnit *SU = &DAG->SUnits[i];
1190 unsigned Color = CurrentColoring[SU->NodeNum];
1197 CurrentBlocks[RealID[Color]]->addUnit(SU);
1198 Node2CurrentBlock[SU->NodeNum] = RealID[Color];
1203 SUnit *SU = &DAG->SUnits[i];
1205 for (SDep& SuccDep : SU->Succs) {
1213 for (SDep& PredDep : SU->Preds) {
1321 for (SUnit* SU : SUs) {
1322 MachineInstr *MI = SU->getInstr();
1746 for (SUnit* SU : SUs)
1747 Res.SUs.push_back(SU->NodeNum);
1787 SUnit *SU = &SUnits[ScheduledSUnits[i]];
1791 for (SDep& PredDep : SU->Preds) {
1803 if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
1814 ScheduledSUnits[BestPos] = SU->NodeNum;
1815 ScheduledSUnitsInv[SU->NodeNum] = BestPos;
1824 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) {
1826 for (SDep& SuccDep : SU->Succs) {
1841 ScheduledSUnits[MinPos] = SU->NodeNum;
1842 ScheduledSUnitsInv[SU->NodeNum] = MinPos;
1915 SUnit *SU = &SUnits[i];
1918 if (SITII->isLowLatencyInstruction(*SU->getInstr())) {
1921 if (SITII->getMemOperandWithOffset(*SU->getInstr(), BaseLatOp, OffLatReg,
1924 } else if (SITII->isHighLatencyDef(SU->getInstr()->getOpcode()))
1990 SUnit *SU = &SUnits[I];
1992 scheduleMI(SU, true);
1994 LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
1995 << *SU->getInstr());