Searched refs:REG (Results 1 - 25 of 476) sorted by relevance

1234567891011>>

/openbsd-current/gnu/usr.bin/binutils/opcodes/
H A Dm88k-dis.c37 {0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0} },
38 {0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0} },
39 {0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0} },
40 {0xf400c400,"jmp.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JMP , 0,0,1,0,0,0,1,1,0,0,0,0} },
45 {0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0,0,0,1,0,0,0,0} },
46 {0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0,0,1,1,0,0,0,0} },
47 {0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0,0,0,1,0,0,0,0} },
48 {0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0,0,1,1,0,0,0,0} },
49 {0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0,0,0,1,0,0,0,0} },
50 {0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{
[all...]
H A Darc-opc.c118 'r' REG generic register value, for register table
271 #define REG (MODDOT + 1) macro
275 #define AUXREG (REG + 1)
361 { "r0", 0, REG, 0 }, { "r1", 1, REG, 0 }, { "r2", 2, REG, 0 },
362 { "r3", 3, REG, 0 }, { "r4", 4, REG, 0 }, { "r5", 5, REG, 0 },
363 { "r6", 6, REG,
[all...]
/openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/
H A Dm88k-dis.c40 {0xf400c800,"jsr ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JSR , 0,0,1,0,0,0,0,1,0,0,0,0} },
41 {0xf400cc00,"jsr.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JSR , 0,0,1,0,0,0,1,1,0,0,0,0} },
42 {0xf400c000,"jmp ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {2,2,NA,JMP , 0,0,1,0,0,0,0,1,0,0,0,0} },
43 {0xf400c400,"jmp.n ",{0,5,REG} ,NO_OPERAND ,NO_OPERAND , {1,1,NA,JMP , 0,0,1,0,0,0,1,1,0,0,0,0} },
48 {0xd0000000,"bb0 ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB0, i16bit,0,1,0,0,0,0,1,0,0,0,0} },
49 {0xd4000000,"bb0.n ",{21,5,HEX} ,{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB0, i16bit,0,1,0,0,0,1,1,0,0,0,0} },
50 {0xd8000000,"bb1 ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{2,2,NA,BB1, i16bit,0,1,0,0,0,0,1,0,0,0,0} },
51 {0xdc000000,"bb1.n ",{21,5,HEX},{16,5,REG} ,{0,16,PCREL},{1,1,NA,BB1, i16bit,0,1,0,0,0,1,1,0,0,0,0} },
52 {0xf000d000,"tb0 ",{21,5,HEX} ,{16,5,REG} ,{0,10,HEX}, {2,2,NA,TB0 , i10bit,0,1,0,0,0,0,1,0,0,0,0} },
53 {0xf000d800,"tb1 ",{21,5,HEX} ,{16,5,REG} ,{
[all...]
/openbsd-current/sys/arch/sh/sh/
H A Ddevreg.c101 SH ## x ## REG(TRA); \
102 SH ## x ## REG(EXPEVT); \
103 SH ## x ## REG(INTEVT); \
105 SH ## x ## REG(BARA); \
106 SH ## x ## REG(BAMRA); \
107 SH ## x ## REG(BASRA); \
108 SH ## x ## REG(BBRA); \
109 SH ## x ## REG(BARB); \
110 SH ## x ## REG(BAMRB); \
111 SH ## x ## REG(BASR
[all...]
/openbsd-current/gnu/usr.bin/binutils/include/opcode/
H A Di960.h40 #define REG 3 macro
50 /* Masks for the mode bits in REG format instructions */
55 /* Generate the 12-bit opcode for a REG format instruction by placing the
62 /* Generate a template for a REG format instruction: place the opcode bits
70 * The information is also useful to us because some 1-operand REG instructions
71 * use the src1 field, others the dst field; and some 2-operand REG instructions
139 char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */
284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } },
285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } },
286 { R_3(0x582), "andnot", I_BASE, REG,
[all...]
/openbsd-current/gnu/usr.bin/binutils-2.17/include/opcode/
H A Di960.h40 #define REG 3 macro
50 /* Masks for the mode bits in REG format instructions */
55 /* Generate the 12-bit opcode for a REG format instruction by placing the
62 /* Generate a template for a REG format instruction: place the opcode bits
70 * The information is also useful to us because some 1-operand REG instructions
71 * use the src1 field, others the dst field; and some 2-operand REG instructions
139 char format; /* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ */
284 { R_3(0x580), "notbit", I_BASE, REG, 3, { RSL,RSL,RS } },
285 { R_3(0x581), "and", I_BASE, REG, 3, { RSL,RSL,RS } },
286 { R_3(0x582), "andnot", I_BASE, REG,
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A):
99 case REG(DC_GPIO_HPD_A):
126 case REG(DC_GPIO_SYNCA_A):
140 /* REG(DC_GPIO_GENLK_MASK */
141 case REG(DC_GPIO_GENLK_A):
165 case REG(DC_GPIO_DDC1_A):
168 case REG(DC_GPIO_DDC2_A):
171 case REG(DC_GPIO_DDC3_A):
174 case REG(DC_GPIO_DDC4_
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A):
99 case REG(DC_GPIO_HPD_A):
126 case REG(DC_GPIO_SYNCA_A):
140 /* REG(DC_GPIO_GENLK_MASK */
141 case REG(DC_GPIO_GENLK_A):
165 case REG(DC_GPIO_DDC1_A):
168 case REG(DC_GPIO_DDC2_A):
171 case REG(DC_GPIO_DDC3_A):
174 case REG(DC_GPIO_DDC4_
[all...]
/openbsd-current/gnu/llvm/lldb/source/Plugins/Process/FreeBSDKernel/
H A DRegisterContextFreeBSDKernel_x86_64.cpp62 #define REG(x) \ macro
67 REG(r15);
68 REG(r14);
69 REG(r13);
70 REG(r12);
71 REG(rbp);
72 REG(rsp);
73 REG(rbx);
74 REG(rip);
76 #undef REG macro
[all...]
H A DRegisterContextFreeBSDKernel_i386.cpp60 #define REG(x) \ macro
65 REG(edi);
66 REG(esi);
67 REG(ebp);
68 REG(esp);
69 REG(eip);
71 #undef REG macro
/openbsd-current/sys/arch/luna88k/stand/boot/
H A Dsio.c96 int rr0 = sioreg(REG(unit, RR0), 0);
97 int rr1 = sioreg(REG(unit, RR1), 0);
104 sioreg(REG(unit, WR0), WR0_ERRRST); /* Channel-A Error Reset */
188 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0);
193 while ((sioreg(REG(unit, RR0), 0) & RR0_TXEMPTY) == 0);
204 sioreg(REG(0, WR0), WR0_CHANRST); /* Channel-A Reset */
209 sioreg(REG(0, WR0), WR0_RSTINT); /* Reset E/S Interrupt */
210 sioreg(REG(0, WR4), WR4_BAUD96 | WR4_STOP1 | WR4_NPARITY); /* Tx/Rx */
211 sioreg(REG(0, WR3), WR3_RX8BIT | WR3_RXENBL); /* Rx */
212 sioreg(REG(
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dcn30/
H A Dhw_translate_dcn30.c61 #undef REG macro
62 #define REG(reg_name)\ macro
80 case REG(DC_GPIO_GENERIC_A):
110 case REG(DC_GPIO_HPD_A):
136 /* REG(DC_GPIO_GENLK_MASK */
137 case REG(DC_GPIO_GENLK_A):
162 case REG(DC_GPIO_DDC1_A):
165 case REG(DC_GPIO_DDC2_A):
168 case REG(DC_GPIO_DDC3_A):
171 case REG(DC_GPIO_DDC4_
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dcn20/
H A Dhw_translate_dcn20.c54 #undef REG macro
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A):
103 case REG(DC_GPIO_HPD_A):
129 /* REG(DC_GPIO_GENLK_MASK */
130 case REG(DC_GPIO_GENLK_A):
155 case REG(DC_GPIO_DDC1_A):
158 case REG(DC_GPIO_DDC2_A):
161 case REG(DC_GPIO_DDC3_A):
164 case REG(DC_GPIO_DDC4_
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_dpp_cm.c33 #define REG(reg)\ macro
247 gam_regs.start_cntl_b = REG(CM_GAMCOR_RAMB_START_CNTL_B);
248 gam_regs.start_cntl_g = REG(CM_GAMCOR_RAMB_START_CNTL_G);
249 gam_regs.start_cntl_r = REG(CM_GAMCOR_RAMB_START_CNTL_R);
250 gam_regs.start_slope_cntl_b = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_B);
251 gam_regs.start_slope_cntl_g = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_G);
252 gam_regs.start_slope_cntl_r = REG(CM_GAMCOR_RAMB_START_SLOPE_CNTL_R);
253 gam_regs.start_end_cntl1_b = REG(CM_GAMCOR_RAMB_END_CNTL1_B);
254 gam_regs.start_end_cntl2_b = REG(CM_GAMCOR_RAMB_END_CNTL2_B);
255 gam_regs.start_end_cntl1_g = REG(CM_GAMCOR_RAMB_END_CNTL1_
[all...]
H A Ddcn30_dwb_cm.c36 #define REG(reg)\ macro
89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B);
90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G);
91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R);
92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B);
93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G);
94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R);
95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B);
96 gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G);
97 gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_
[all...]
/openbsd-current/sys/dev/pci/drm/i915/gt/
H A Dintel_lrc.c36 * number of registers. They are set by using the REG/REG16 macros: the former
54 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) macro
110 REG(0x034),
111 REG(0x030),
112 REG(0x038),
113 REG(0x03c),
114 REG(0x168),
115 REG(0x140),
116 REG(0x110),
117 REG(
678 #undef REG macro
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dcn315/
H A Dhw_translate_dcn315.c54 #undef REG macro
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A):
103 case REG(DC_GPIO_HPD_A):
129 /* REG(DC_GPIO_GENLK_MASK */
130 case REG(DC_GPIO_GENLK_A):
155 case REG(DC_GPIO_DDC1_A):
158 case REG(DC_GPIO_DDC2_A):
161 case REG(DC_GPIO_DDC3_A):
164 case REG(DC_GPIO_DDC4_
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dcn32/
H A Dhw_translate_dcn32.c52 #undef REG macro
53 #define REG(reg_name)\ macro
71 case REG(DC_GPIO_GENERIC_A):
98 case REG(DC_GPIO_HPD_A):
121 /* REG(DC_GPIO_GENLK_MASK */
122 case REG(DC_GPIO_GENLK_A):
146 case REG(DC_GPIO_DDC1_A):
149 case REG(DC_GPIO_DDC2_A):
152 case REG(DC_GPIO_DDC3_A):
155 case REG(DC_GPIO_DDC4_
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/gpio/dcn21/
H A Dhw_translate_dcn21.c54 #undef REG macro
55 #define REG(reg_name)\ macro
72 case REG(DC_GPIO_GENERIC_A):
106 case REG(DC_GPIO_HPD_A):
132 /* REG(DC_GPIO_GENLK_MASK */
133 case REG(DC_GPIO_GENLK_A):
158 case REG(DC_GPIO_DDC1_A):
161 case REG(DC_GPIO_DDC2_A):
164 case REG(DC_GPIO_DDC3_A):
167 case REG(DC_GPIO_DDC4_
[all...]
/openbsd-current/gnu/usr.bin/binutils-2.17/gas/config/
H A Dbfin-parse.y396 %token REG
523 %type <reg> REG
717 | REG ASSIGN LPAREN a_plusassign REG_A RPAREN
747 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16P LPAREN REG
748 COLON expr COMMA REG COLON expr RPAREN aligndir
763 | LPAREN REG COMMA REG RPAREN ASSIGN BYTEOP16M LPAREN REG COLO
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCReturnProtectorLowering.cpp40 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); local
66 // Load the random cookie value into REG
67 BuildMI(MBB, MI, MBBDL, TII->get(PPC::ADDIStocHA8), REG)
70 BuildMI(MBB, MI, MBBDL, TII->get(PPC::LD), REG)
72 .addReg(REG);
74 BuildMI(MBB, MI, MBBDL, TII->get(XOR), REG)
75 .addReg(REG)
82 BuildMI(MBB, MI, MBBDL, TII->get(PPC::RETGUARD_LOAD_PC), REG)
85 // Get the random cookie address into REG
86 BuildMI(MBB, MI, MBBDL, TII->get(PPC::RETGUARD_LOAD_GOT), REG)
122 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); local
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64ReturnProtectorLowering.cpp40 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); local
42 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::ADRP), REG)
44 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::LDRXui), REG)
45 .addReg(REG)
47 BuildMI(MBB, MI, MBBDL, TII->get(AArch64::EORXrr), REG)
48 .addReg(REG)
58 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); local
61 // REG holds the cookie we calculated in prologue. We use X9 as a
62 // scratch reg to pull the random data. XOR REG with LR should yield
63 // the random data again. Compare REG wit
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/X86/
H A DX86ReturnProtectorLowering.cpp39 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); local
41 BuildMI(MBB, MI, MBBDL, TII->get(X86::MOV64rm), REG)
47 addDirectMem(BuildMI(MBB, MI, MBBDL, TII->get(X86::XOR64rm), REG).addReg(REG),
57 unsigned REG = MF.getFrameInfo().getReturnProtectorRegister(); local
59 addDirectMem(BuildMI(MBB, MI, MBBDL, TII->get(X86::XOR64rm), REG).addReg(REG),
62 .addReg(REG)
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/
H A Ddcn10_dpp_cm.c42 #define REG(reg)\ macro
125 gam_regs.csc_c11_c12 = REG(CM_GAMUT_REMAP_C11_C12);
126 gam_regs.csc_c33_c34 = REG(CM_GAMUT_REMAP_C33_C34);
135 gam_regs.csc_c11_c12 = REG(CM_COMA_C11_C12);
136 gam_regs.csc_c33_c34 = REG(CM_COMA_C33_C34);
145 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C12);
146 gam_regs.csc_c33_c34 = REG(CM_COMB_C33_C34);
220 gam_regs.csc_c11_c12 = REG(CM_OCSC_C11_C12);
221 gam_regs.csc_c33_c34 = REG(CM_OCSC_C33_C34);
225 gam_regs.csc_c11_c12 = REG(CM_COMB_C11_C1
[all...]
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn301/
H A Ddcn301_hwseq.c35 #define REG(reg)\ macro

Completed in 312 milliseconds

1234567891011>>