1/* $OpenBSD: devreg.c,v 1.3 2016/03/05 17:16:33 tobiasu Exp $ */ 2/* $NetBSD: devreg.c,v 1.6 2006/03/04 01:13:35 uwe Exp $ */ 3 4/*- 5 * Copyright (c) 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/param.h> 31 32#include <sh/cache_sh3.h> 33#include <sh/cache_sh4.h> 34#include <sh/mmu_sh3.h> 35#include <sh/mmu_sh4.h> 36#include <sh/trap.h> 37 38#include <sh/ubcreg.h> 39#include <sh/rtcreg.h> 40#include <sh/tmureg.h> 41 42/* MMU */ 43uint32_t __sh_PTEH; 44uint32_t __sh_TTB; 45uint32_t __sh_TEA; 46uint32_t __sh_TRA; 47uint32_t __sh_EXPEVT; 48uint32_t __sh_INTEVT; 49 50/* UBC */ 51uint32_t __sh_BARA; 52uint32_t __sh_BAMRA; 53uint32_t __sh_BASRA; 54uint32_t __sh_BBRA; 55uint32_t __sh_BARB; 56uint32_t __sh_BAMRB; 57uint32_t __sh_BASRB; 58uint32_t __sh_BBRB; 59uint32_t __sh_BDRB; 60uint32_t __sh_BDMRB; 61uint32_t __sh_BRCR; 62 63/* RTC */ 64uint32_t __sh_R64CNT; 65uint32_t __sh_RSECCNT; 66uint32_t __sh_RMINCNT; 67uint32_t __sh_RHRCNT; 68uint32_t __sh_RWKCNT; 69uint32_t __sh_RDAYCNT; 70uint32_t __sh_RMONCNT; 71uint32_t __sh_RYRCNT; 72uint32_t __sh_RSECAR; 73uint32_t __sh_RMINAR; 74uint32_t __sh_RHRAR; 75uint32_t __sh_RWKAR; 76uint32_t __sh_RDAYAR; 77uint32_t __sh_RMONAR; 78uint32_t __sh_RCR1; 79uint32_t __sh_RCR2; 80 81/* TMU */ 82uint32_t __sh_TOCR; 83uint32_t __sh_TSTR; 84uint32_t __sh_TCOR0; 85uint32_t __sh_TCNT0; 86uint32_t __sh_TCR0; 87uint32_t __sh_TCOR1; 88uint32_t __sh_TCNT1; 89uint32_t __sh_TCR1; 90uint32_t __sh_TCOR2; 91uint32_t __sh_TCNT2; 92uint32_t __sh_TCR2; 93uint32_t __sh_TCPR2; 94 95#define SH3REG(x) __sh_ ## x = SH3_ ## x 96#define SH4REG(x) __sh_ ## x = SH4_ ## x 97 98#define SHREG(x) \ 99do { \ 100/* Exception */ \ 101SH ## x ## REG(TRA); \ 102SH ## x ## REG(EXPEVT); \ 103SH ## x ## REG(INTEVT); \ 104/* UBC */ \ 105SH ## x ## REG(BARA); \ 106SH ## x ## REG(BAMRA); \ 107SH ## x ## REG(BASRA); \ 108SH ## x ## REG(BBRA); \ 109SH ## x ## REG(BARB); \ 110SH ## x ## REG(BAMRB); \ 111SH ## x ## REG(BASRB); \ 112SH ## x ## REG(BBRB); \ 113SH ## x ## REG(BDRB); \ 114SH ## x ## REG(BDMRB); \ 115SH ## x ## REG(BRCR); \ 116/* MMU */ \ 117SH ## x ## REG(PTEH); \ 118SH ## x ## REG(TEA); \ 119SH ## x ## REG(TTB); \ 120/* RTC */ \ 121SH ## x ## REG(R64CNT); \ 122SH ## x ## REG(RSECCNT); \ 123SH ## x ## REG(RMINCNT); \ 124SH ## x ## REG(RHRCNT); \ 125SH ## x ## REG(RWKCNT); \ 126SH ## x ## REG(RDAYCNT); \ 127SH ## x ## REG(RMONCNT); \ 128SH ## x ## REG(RYRCNT); \ 129SH ## x ## REG(RSECAR); \ 130SH ## x ## REG(RMINAR); \ 131SH ## x ## REG(RHRAR); \ 132SH ## x ## REG(RWKAR); \ 133SH ## x ## REG(RDAYAR); \ 134SH ## x ## REG(RMONAR); \ 135SH ## x ## REG(RCR1); \ 136SH ## x ## REG(RCR2); \ 137/* TMU */ \ 138SH ## x ## REG(TOCR); \ 139SH ## x ## REG(TSTR); \ 140SH ## x ## REG(TCOR0); \ 141SH ## x ## REG(TCNT0); \ 142SH ## x ## REG(TCR0); \ 143SH ## x ## REG(TCOR1); \ 144SH ## x ## REG(TCNT1); \ 145SH ## x ## REG(TCR1); \ 146SH ## x ## REG(TCOR2); \ 147SH ## x ## REG(TCNT2); \ 148SH ## x ## REG(TCR2); \ 149SH ## x ## REG(TCPR2); \ 150} while (/*CONSTCOND*/0) 151 152void 153sh_devreg_init(void) 154{ 155 if (CPU_IS_SH3) 156 SHREG(3); 157 158 if (CPU_IS_SH4) 159 SHREG(4); 160} 161