Searched refs:OrigMI (Results 1 - 9 of 9) sorted by relevance
/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | GCNDPPCombine.cpp | 63 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI, 68 MachineInstr *createDPPInst(MachineInstr &OrigMI, MachineInstr &MovMI, 194 MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, argument 204 auto OrigOp = OrigMI.getOpcode(); 224 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI, 225 OrigMI.getDebugLoc(), TII->get(DPPOp)) 226 .setMIFlags(OrigMI.getFlags()); 231 if (auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst)) { 235 if (auto *SDst = TII->getNamedOperand(OrigMI, AMDGP 448 createDPPInst( MachineInstr &OrigMI, MachineInstr &MovMI, RegSubRegPair CombOldVGPR, MachineOperand *OldOpndValue, bool CombBCZ, bool IsShrinkable) const argument 598 auto &OrigMI = *Use->getParent(); local [all...] |
/openbsd-current/gnu/llvm/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 104 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 106 bool LiveRangeEdit::allUsesAvailableAt(const MachineInstr *OrigMI, argument 111 for (const MachineOperand &MO : OrigMI->operands()) { 129 // It would be incorrect if OrigMI redefines the register. 168 assert(RM.OrigMI && "No defining instruction for remattable value"); 169 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); 172 if (cheapAsAMove && !TII.isAsCheapAsAMove(*RM.OrigMI)) 176 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) 190 assert(RM.OrigMI && "Invalid remat"); 191 TII.reMaterialize(MBB, MI, DestReg, SubIdx, *RM.OrigMI, tr [all...] |
H A D | InlineSpiller.cpp | 609 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); 627 if (RM.OrigMI->canFoldAsLoad() && 628 foldMemoryOperand(Ops, RM.OrigMI)) { 645 // Finally we can rematerialize OrigMI before MI. 649 // We take the DebugLoc from MI, since OrigMI may be attributed to a
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H A D | ModuloSchedule.cpp | 1163 MachineInstr *OrigMI = OrigInstr->second; local 1164 int StageSched = Schedule.getStage(OrigMI); 1165 int CycleSched = Schedule.getCycle(OrigMI); 1173 (CyclePhi <= CycleSched || OrigMI->isPHI()))
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H A D | SplitKit.cpp | 600 RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def);
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H A D | RegisterCoalescer.cpp | 1349 RM.OrigMI = DefMI;
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/openbsd-current/gnu/llvm/llvm/lib/Target/X86/ |
H A D | X86FixupBWInsts.cpp | 84 /// that super register is dead just prior to \p OrigMI, and false if not. 85 bool getSuperRegDestIfDead(MachineInstr *OrigMI, 186 /// Check if after \p OrigMI the only portion of super register 187 /// of the destination register of \p OrigMI that is alive is that 191 bool FixupBWInstPass::getSuperRegDestIfDead(MachineInstr *OrigMI, argument 194 Register OrigDestReg = OrigMI->getOperand(0).getReg(); 253 unsigned Opc = OrigMI->getOpcode(); (void)Opc; 262 for (auto &MO: OrigMI->implicit_operands()) {
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/openbsd-current/gnu/llvm/llvm/include/llvm/CodeGen/ |
H A D | LiveRangeEdit.h | 191 MachineInstr *OrigMI = nullptr; // Instruction defining OrigVNI. It contains member in struct:llvm::LiveRangeEdit::Remat 197 /// allUsesAvailableAt - Return true if all registers used by OrigMI at 199 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/ |
H A D | RISCVInstrInfo.cpp | 2540 bool RISCVInstrInfo::hasAllNBitUsers(const MachineInstr &OrigMI, argument 2547 Worklist.push_back(std::make_pair(&OrigMI, OrigBits));
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