Searched refs:DISPLAY_MMIO_BASE (Results 1 - 3 of 3) sorted by relevance

/openbsd-current/sys/dev/pci/drm/i915/display/
H A Dintel_dp_aux_regs.h16 #define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
17 #define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
19 #define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
20 #define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
H A Dintel_display_reg_defs.h11 #define DISPLAY_MMIO_BASE(dev_priv) (DISPLAY_INFO(dev_priv)->mmio_offset) macro
41 DISPLAY_MMIO_BASE(dev_priv) + (reg))
44 DISPLAY_MMIO_BASE(dev_priv) + (reg))
47 DISPLAY_MMIO_BASE(dev_priv) + (reg))
/openbsd-current/sys/dev/pci/drm/i915/
H A Di915_reg.h1412 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
1413 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
1414 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
1511 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
1512 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
1513 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
1585 #define DSPCLK_GATE_D(__i915) _MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
1743 #define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
2148 #define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
2178 #define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_pri
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