| /openbsd-current/gnu/usr.bin/binutils/opcodes/ |
| H A D | m10200-opc.c | 52 #define AM0 (AN1+1)
56 #define AM1 (AM0+1)
168 { "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}},
180 { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
181 { "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}},
182 { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
183 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
184 { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
194 { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}},
195 { "mov", 0x5000, 0xf000, FMT_2, {AM0, ME
51 #define AM0 macro
[all...] |
| H A D | m10300-opc.c | 66 #define AM0 (AN2+1)
70 #define AM1 (AM0+1)
459 { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
462 { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
472 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
473 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
476 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
477 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
478 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
480 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN
65 #define AM0 macro
[all...] |
| /openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/ |
| H A D | m10200-opc.c | 52 #define AM0 (AN1+1)
56 #define AM1 (AM0+1)
168 { "mov", 0xf270, 0xfff0, FMT_4, {AN1, AM0}},
180 { "mov", 0x7000, 0xf000, FMT_2, {MEM2(SD8,AN1), AM0}},
181 { "mov", 0x7000, 0xf000, FMT_2, {MEM(AN1), AM0}},
182 { "mov", 0xf7b00000, 0xfff00000, FMT_6, {MEM2(SD16, AN1), AM0}},
183 { "mov", 0xf4f00000, 0xfff00000, FMT_7, {MEM2(IMM24,AN1), AM0}},
184 { "mov", 0xf100, 0xffc0, FMT_4, {MEM2(DI, AN1), AM0}},
194 { "mov", 0x5000, 0xf000, FMT_2, {AM0, MEM2(SD8, AN1)}},
195 { "mov", 0x5000, 0xf000, FMT_2, {AM0, ME
51 #define AM0 macro
[all...] |
| H A D | m10300-opc.c | 67 #define AM0 (AN2+1)
71 #define AM1 (AM0+1)
460 { "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
463 { "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
473 { "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
474 { "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
477 { "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
478 { "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
479 { "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
481 { "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN
66 #define AM0 macro
[all...] |