/openbsd-current/gnu/usr.bin/clang/include/llvm/Frontend/OpenACC/ |
H A D | Makefile | 7 DEFS= ACC.h.inc \ 8 ACC.inc 18 ACC.h.inc: ${LLVM_SRCS}/include/llvm/Frontend/OpenACC/ACC.td 25 ACC.inc: ${LLVM_SRCS}/include/llvm/Frontend/OpenACC/ACC.td
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/openbsd-current/gnu/usr.bin/binutils-2.17/include/opcode/ |
H A D | maxq.h | 322 #define ACC MOD9 /* For the module containing the 16 accumulators. */ macro 394 /* The 16 accumulator registers : ACC[0h-Fh] */ 396 "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20}, 398 "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20}, 400 "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20}, 402 "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16 [all...] |
/openbsd-current/gnu/usr.bin/clang/libLLVMFrontendOpenACC/ |
H A D | Makefile | 9 SRCS+= ACC.cpp
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/openbsd-current/gnu/llvm/clang/tools/libclang/ |
H A D | CXCompilationDatabase.cpp | 81 AllocatedCXCompileCommands *ACC = 84 return ACC->CCmd.size(); 93 AllocatedCXCompileCommands *ACC = 96 if (I >= ACC->CCmd.size()) 99 return &ACC->CCmd[I];
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/openbsd-current/gnu/usr.bin/binutils/gas/config/ |
H A D | m68k-parse.h | 87 ACC, /* Accumulator Reg */ enumerator in enum:m68k_register
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/openbsd-current/gnu/usr.bin/binutils-2.17/gas/config/ |
H A D | m68k-parse.h | 87 ACC, /* Accumulator Reg0 (EMAC or ACC on MAC). */ enumerator in enum:m68k_register
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H A D | tc-m68k.c | 1636 if (opP->reg != ACC) 1641 if (opP->reg != ACC && opP->reg != ACC1 2919 install_operand (s[1], opP->reg - ACC); 3714 { "acc", ACC }, 3715 { "acc0", ACC },
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/openbsd-current/gnu/usr.bin/binutils/opcodes/ |
H A D | m32r-opc.c | 659 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 671 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 683 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 695 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 713 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 725 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 737 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 749 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
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H A D | m32r-opinst.c | 319 { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, 322 { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, 336 { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
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/openbsd-current/gnu/llvm/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineCXX.cpp | 326 const auto *ACC = cast<ArgumentConstructionContext>(CC); local 327 const Expr *E = ACC->getCallLikeExpr(); 328 unsigned Idx = ACC->getIndex(); 494 const auto *ACC = cast<ArgumentConstructionContext>(CC); local 495 if (const auto *BTE = ACC->getCXXBindTemporaryExpr()) 499 State, {ACC->getCallLikeExpr(), ACC->getIndex()}, LCtx, V);
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/openbsd-current/gnu/usr.bin/binutils-2.17/opcodes/ |
H A D | m32r-opc.c | 657 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 669 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 681 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 693 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 711 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 723 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 735 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } }, 747 { { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 } },
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H A D | m32r-opinst.c | 319 { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, 322 { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 }, 336 { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
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/openbsd-current/sys/dev/pci/drm/amd/amdkfd/ |
H A D | cwsr_trap_handler_gfx9.asm | 652 // Save ACC VGPRs 655 // ACC VGPR count may differ from ARCH VGPR count. 764 // Save ARCH VGPRs 4-N, then all ACC VGPRs, then ARCH VGPRs 0-3. 787 // ACC VGPR count may differ from ARCH VGPR count. 795 // ACC VGPRs at offset: size(ARCH VGPRs) 1031 s_lshl_b32 s_vgpr_size_byte, s_vgpr_size_byte, 1 // Double size for ACC VGPRs 1047 // VGPR count includes ACC VGPRs, use ACC VGPR offset for ARCH VGPR count. 1065 // ACC VGPR count = VGPR count - ARCH VGPR count.
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/openbsd-current/gnu/usr.bin/perl/lib/unicore/To/ |
H A D | Bmg.pl | 362 2ACB 2ACC 363 2ACC 2ACB
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H A D | InSC.pl | 105 ACB ACC Vowel_Dependent
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H A D | InPC.pl | 75 ACB ACC Right
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H A D | GCB.pl | 102 ACB ACC SpacingMark
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/openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.h | 209 static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \
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/openbsd-current/gnu/usr.bin/perl/cpan/Unicode-Collate/Collate/CJK/ |
H A D | JISX0208.pm | 71 7FF0 809D 8266 839E 89B3 8ACC 8CAB 9084 9451 9593 103 517C 5238 5263 55A7 570F 5805 5ACC 5EFA 61B2 61F8
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H A D | Stroke.pm | 251 7ACC 7ACD 7CFA 7CFB 7EB6 7EAC 7EAD 7EAE 7EAF 7EB0 1227 5ACC 5ACD 5ACE 5AD0 5AD1 5AD2 5AD3 5AD4 1723 8AC4 8AC5 8AC6 8AC7 8AC8 8AC9 8ACA 8ACB 8ACC 8ACD 2130 28A9A 28A9B 28A9C 28AC0 28AC6 28ACB 28ACC 28ACE 956C 956D 2166 3C00 3C01 3C02 3C04 6ACB 6ACC 6ACD 6ACE 6ACF 6AD0 2292 9ACA 9ACB 9ACC 9B10 9B11 9B12 9B13 9B2A
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H A D | GB2312.pm | 325 8237 95F2 6D8E 5F26 5ACC 663E 9669 73B0 732E 53BF 700 9ACB 9ACC 9AD1 9B45 9B43 9B47 9B49 9B48 9B4D 9B51
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H A D | Zhuyin.pm | 147 6448 6BA1 8191 9AE9 64EF 9B02 6BAF 81CF 9ACC 9B13 621 3A02 8463 58A5 7BBD 8ACC 5B1E 23FC5 856B 61C2 1885 86DD 9591 9592 9E47 5ACC 8858 929C 5AFA 5AFB 61AA 2239 4E8D 5904 7ACC 6035 62C0 7ECC 8C56 67F7 6B2A 7AD0 2881 6EFA 6182 512A 5698 7000 913E 6ACC 7E8B 8030
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H A D | Pinyin.pm | 161 6448 6BA1 8191 9AE9 64EF 9B02 6BAF 81CF 9ACC 9B13 321 4E8D 5904 7ACC 6035 62C0 7ECC 8C56 67F7 6B2A 7AD0 499 8463 58A5 5B1E 61C2 7BBD 856B 8ACC 2401 9591 9592 9E47 5ACC 8858 7509 929C 5AFA 5AFB 61AA 2676 6EFA 6182 512A 913E 5698 7000 6ACC 7E8B 8030
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/openbsd-current/gnu/llvm/clang/lib/Analysis/ |
H A D | CFG.cpp | 5729 const auto *ACC = cast<ArgumentConstructionContext>(CC); local 5730 if (const Stmt *BTE = ACC->getCXXBindTemporaryExpr()) { 5735 Helper.handledStmt(const_cast<Expr *>(ACC->getCallLikeExpr()), OS); 5736 OS << "+" << ACC->getIndex();
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/openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 3095 MCRegister ACC = MI.getOperand(0).getReg(); 3097 if (ACC - PPC::ACC0 != UACC - PPC::UACC0) { 3099 MCRegister DstVSR = PPC::VSL0 + (ACC - PPC::ACC0) * 4;
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