Searched refs:pll0 (Results 1 - 2 of 2) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/avr32/mach-at32ap/
H A Dat32ap7000.c158 static struct clk pll0 = { variable in typeref:struct:clk
159 .name = "pll0",
170 * The main clock can be either osc0 or pll0. The boot loader may
387 else if (parent == &osc0 || parent == &pll0)
392 if (parent == &pll0 || parent == &pll1)
414 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
986 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
987 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1062 &pll0,
1120 main_clock = &pll0;
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/shared/
H A Dhndpmu.c4152 uint32 freq_tgt, pll0; local
4171 pll0 = R_REG(osh, &cc->pllcontrol_data);
4173 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
4215 pll0 = (pll0 & ~PMU15_PLL_PC0_FREQTGT_MASK) | (xt->freq_tgt << PMU15_PLL_PC0_FREQTGT_SHIFT);
4216 W_REG(osh, &cc->pllcontrol_data, pll0);
4246 uint32 freq_tgt = 0, pll0 = 0; local
4254 pll0 = R_REG(osh, &cc->pllcontrol_data);
4255 freq_tgt = (pll0 & PMU15_PLL_PC0_FREQTGT_MASK) >> PMU15_PLL_PC0_FREQTGT_SHIFT;
4283 uint32 freq_tgt, pll0; local
5114 si_pmu5_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m) argument
5166 si_4706_pmu_clock(si_t *sih, osl_t *osh, chipcregs_t *cc, uint pll0, uint m) argument
6513 uint32 pll0; local
[all...]

Completed in 97 milliseconds