Searched refs:new_line (Results 1 - 10 of 10) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/wan/
H A Dc101.c226 sync_serial_settings new_line; local
259 if (copy_from_user(&new_line, line, size))
262 if (new_line.clock_type != CLOCK_EXT &&
263 new_line.clock_type != CLOCK_TXFROMRX &&
264 new_line.clock_type != CLOCK_INT &&
265 new_line.clock_type != CLOCK_TXINT)
268 if (new_line.loopback != 0 && new_line.loopback != 1)
271 memcpy(&port->settings, &new_line, size); /* Update settings */
H A Dpci200syn.c202 sync_serial_settings new_line; local
231 if (copy_from_user(&new_line, line, size))
234 if (new_line.clock_type != CLOCK_EXT &&
235 new_line.clock_type != CLOCK_TXFROMRX &&
236 new_line.clock_type != CLOCK_INT &&
237 new_line.clock_type != CLOCK_TXINT)
240 if (new_line.loopback != 0 && new_line.loopback != 1)
243 memcpy(&port->settings, &new_line, size); /* Update settings */
H A Dn2.c252 sync_serial_settings new_line; local
280 if (copy_from_user(&new_line, line, size))
283 if (new_line.clock_type != CLOCK_EXT &&
284 new_line.clock_type != CLOCK_TXFROMRX &&
285 new_line.clock_type != CLOCK_INT &&
286 new_line.clock_type != CLOCK_TXINT)
289 if (new_line.loopback != 0 && new_line.loopback != 1)
292 memcpy(&port->settings, &new_line, size); /* Update settings */
H A Dpc300too.c211 sync_serial_settings new_line; local
257 if (copy_from_user(&new_line, line, size))
260 if (new_line.clock_type != CLOCK_EXT &&
261 new_line.clock_type != CLOCK_TXFROMRX &&
262 new_line.clock_type != CLOCK_INT &&
263 new_line.clock_type != CLOCK_TXINT)
266 if (new_line.loopback != 0 && new_line.loopback != 1)
269 memcpy(&port->settings, &new_line, size); /* Update settings */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/avahi-0.6.25/avahi-dnsconfd/
H A Dmain.c285 static int new_line(const char *l) { function
523 if (new_line(buf) < 0)
534 if (new_line(buf) < 0)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/
H A Dimgresample.c368 uint8_t *new_line, *src_line; local
390 new_line = s->line_buf + ring_y * owidth;
392 h_resample(new_line, owidth,
398 new_line, owidth);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/pcmcia/
H A Dsynclink_cs.c4292 sync_serial_settings new_line; local
4322 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
4323 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
4324 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
4325 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
4326 default: new_line.clock_type = CLOCK_DEFAULT;
4329 new_line.clock_rate = info->params.clock_speed;
4330 new_line.loopback = info->params.loopback ? 1:0;
4332 if (copy_to_user(line, &new_line, size))
4340 if (copy_from_user(&new_line, lin
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/
H A Dsynclink_gt.c1658 sync_serial_settings new_line; local
1687 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1688 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1689 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1690 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1691 default: new_line.clock_type = CLOCK_DEFAULT;
1694 new_line.clock_rate = info->params.clock_speed;
1695 new_line.loopback = info->params.loopback ? 1:0;
1697 if (copy_to_user(line, &new_line, size))
1705 if (copy_from_user(&new_line, lin
[all...]
H A Dsynclink.c7879 sync_serial_settings new_line; local
7909 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7910 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7911 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7912 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7913 default: new_line.clock_type = CLOCK_DEFAULT;
7916 new_line.clock_rate = info->params.clock_speed;
7917 new_line.loopback = info->params.loopback ? 1:0;
7919 if (copy_to_user(line, &new_line, size))
7927 if (copy_from_user(&new_line, lin
[all...]
H A Dsynclinkmp.c1806 sync_serial_settings new_line; local
1836 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1837 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1838 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1839 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1840 default: new_line.clock_type = CLOCK_DEFAULT;
1843 new_line.clock_rate = info->params.clock_speed;
1844 new_line.loopback = info->params.loopback ? 1:0;
1846 if (copy_to_user(line, &new_line, size))
1854 if (copy_from_user(&new_line, lin
[all...]

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