Searched refs:fvco (Results 1 - 8 of 8) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-s3c2410/
H A Dregs-s3c2443-clock.h158 uint64_t fvco; local
168 fvco = (uint64_t)baseclk * (2 * (mdiv + 8));
169 do_div(fvco, pdiv << sdiv);
171 return (unsigned int)fvco;
178 uint64_t fvco; local
188 fvco = (uint64_t)baseclk * (mdiv + 8);
189 do_div(fvco, (pdiv + 2) << sdiv);
191 return (unsigned int)fvco;
H A Dregs-clock.h87 uint64_t fvco; local
97 fvco = (uint64_t)baseclk * (mdiv + 8);
98 do_div(fvco, (pdiv + 2) << sdiv);
100 return (unsigned int)fvco;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/matrox/
H A Dg450_pll.c20 static inline unsigned int g450_vco2f(unsigned char p, unsigned int fvco) { argument
21 return (p & 0x40) ? fvco : fvco >> ((p & 3) + 1);
52 static unsigned int g450_nextpll(CPMINFO const struct matrox_pll_limits* pi, unsigned int* fvco, unsigned int mnp) { argument
54 unsigned int tvco = *fvco;
74 *fvco = tvco;
H A Dmatroxfb_maven.c286 unsigned int fvco; local
289 fvco = matroxfb_PLL_mavenclock(&maven1000_pll, ctl, htotal, vtotal, in, feed, &p, htotal2);
290 if (!fvco)
293 if (fvco <= 100000000)
295 else if (fvco <= 140000000)
297 else if (fvco <= 180000000)
307 unsigned int fvco; local
310 fvco = matroxfb_PLL_calcclock(&maven_pll, freq, fmax, in, feed, &p);
312 if (fvco <= 100000)
314 else if (fvco <
[all...]
H A Dmatroxfb_misc.c161 unsigned int diff, fvco; local
169 fvco = (fxtal * (n + 1)) / (m + 1);
170 if (fvco < fwant)
171 diff = fwant - fvco;
173 diff = fvco - fwant;
179 bestvco = fvco;
H A Dmatroxfb_Ti3026.c283 unsigned int fvco; local
288 fvco = PLL_calcclock(PMINFO freq, fmax, &lin, &lfeed, &lpost);
289 fvco >>= (*post = lpost);
292 return fvco;
H A Dmatroxfb_DAC1064.c37 unsigned int fvco; local
44 fvco = PLL_calcclock(PMINFO freq, fmax, in, feed, &p);
47 if (fvco <= 100000)
49 else if (fvco <= 140000)
51 else if (fvco <= 180000)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/shared/
H A Dhndpmu.c2551 /* the following table is based on 880Mhz fvco */
2798 /* the following table is based on 880Mhz fvco */
2837 /* the following table is based on 1760Mhz fvco */
2874 /* the following table is based on 1440Mhz fvco */
3288 /** returns chip specific default pll fvco frequency */
6598 uint32 xf, ndiv_int, ndiv_frac, fvco, pll_reg, p1_div_scale; local
6646 bcm_uint64_right_shift(&fvco, r_high, r_low, P1_DIV_SCALE_BITS);
6650 return fvco;

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