1/* 2 * 3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400 4 * 5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz> 6 * 7 * Portions Copyright (c) 2001 Matrox Graphics Inc. 8 * 9 * Version: 1.65 2002/08/14 10 * 11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org> 12 * 13 * Contributors: "menion?" <menion@mindless.com> 14 * Betatesting, fixes, ideas 15 * 16 * "Kurt Garloff" <garloff@suse.de> 17 * Betatesting, fixes, ideas, videomodes, videomodes timmings 18 * 19 * "Tom Rini" <trini@kernel.crashing.org> 20 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas 21 * 22 * "Bibek Sahu" <scorpio@dodds.net> 23 * Access device through readb|w|l and write b|w|l 24 * Extensive debugging stuff 25 * 26 * "Daniel Haun" <haund@usa.net> 27 * Testing, hardware cursor fixes 28 * 29 * "Scott Wood" <sawst46+@pitt.edu> 30 * Fixes 31 * 32 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de> 33 * Betatesting 34 * 35 * "Kelly French" <targon@hazmat.com> 36 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es> 37 * Betatesting, bug reporting 38 * 39 * "Pablo Bianucci" <pbian@pccp.com.ar> 40 * Fixes, ideas, betatesting 41 * 42 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es> 43 * Fixes, enhandcements, ideas, betatesting 44 * 45 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp> 46 * PPC betatesting, PPC support, backward compatibility 47 * 48 * "Paul Womar" <Paul@pwomar.demon.co.uk> 49 * "Owen Waller" <O.Waller@ee.qub.ac.uk> 50 * PPC betatesting 51 * 52 * "Thomas Pornin" <pornin@bolet.ens.fr> 53 * Alpha betatesting 54 * 55 * "Pieter van Leuven" <pvl@iae.nl> 56 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de> 57 * G100 testing 58 * 59 * "H. Peter Arvin" <hpa@transmeta.com> 60 * Ideas 61 * 62 * "Cort Dougan" <cort@cs.nmt.edu> 63 * CHRP fixes and PReP cleanup 64 * 65 * "Mark Vojkovich" <mvojkovi@ucsd.edu> 66 * G400 support 67 * 68 * "David C. Hansen" <haveblue@us.ibm.com> 69 * Fixes 70 * 71 * "Ian Romanick" <idr@us.ibm.com> 72 * Find PInS data in BIOS on PowerPC systems. 73 * 74 * (following author is not in any relation with this code, but his code 75 * is included in this driver) 76 * 77 * Based on framebuffer driver for VBE 2.0 compliant graphic boards 78 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de> 79 * 80 * (following author is not in any relation with this code, but his ideas 81 * were used when writing this driver) 82 * 83 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk> 84 * 85 */ 86 87 88#include "matroxfb_misc.h" 89#include <linux/interrupt.h> 90#include <linux/matroxfb.h> 91 92void matroxfb_DAC_out(CPMINFO int reg, int val) { 93 DBG_REG(__FUNCTION__) 94 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); 95 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val); 96} 97 98int matroxfb_DAC_in(CPMINFO int reg) { 99 DBG_REG(__FUNCTION__) 100 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); 101 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG); 102} 103 104void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) { 105 unsigned int pixclock = var->pixclock; 106 107 DBG(__FUNCTION__) 108 109 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */ 110 mt->pixclock = 1000000000 / pixclock; 111 if (mt->pixclock < 1) mt->pixclock = 1; 112 mt->mnp = -1; 113 mt->dblscan = var->vmode & FB_VMODE_DOUBLE; 114 mt->interlaced = var->vmode & FB_VMODE_INTERLACED; 115 mt->HDisplay = var->xres; 116 mt->HSyncStart = mt->HDisplay + var->right_margin; 117 mt->HSyncEnd = mt->HSyncStart + var->hsync_len; 118 mt->HTotal = mt->HSyncEnd + var->left_margin; 119 mt->VDisplay = var->yres; 120 mt->VSyncStart = mt->VDisplay + var->lower_margin; 121 mt->VSyncEnd = mt->VSyncStart + var->vsync_len; 122 mt->VTotal = mt->VSyncEnd + var->upper_margin; 123 mt->sync = var->sync; 124} 125 126int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, 127 unsigned int* in, unsigned int* feed, unsigned int* post) { 128 unsigned int bestdiff = ~0; 129 unsigned int bestvco = 0; 130 unsigned int fxtal = pll->ref_freq; 131 unsigned int fwant; 132 unsigned int p; 133 134 DBG(__FUNCTION__) 135 136 fwant = freq; 137 138#ifdef DEBUG 139 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); 140 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); 141 printk(KERN_ERR "freq: %d\n", freq); 142 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); 143 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); 144 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); 145 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); 146 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); 147 printk(KERN_ERR "fmax: %d\n", fmax); 148#endif 149 for (p = 1; p <= pll->post_shift_max; p++) { 150 if (fwant * 2 > fmax) 151 break; 152 fwant *= 2; 153 } 154 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min; 155 if (fwant > fmax) fwant = fmax; 156 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) { 157 unsigned int m; 158 159 if (fwant < pll->vco_freq_min) break; 160 for (m = pll->in_div_min; m <= pll->in_div_max; m++) { 161 unsigned int diff, fvco; 162 unsigned int n; 163 164 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1; 165 if (n > pll->feed_div_max) 166 break; 167 if (n < pll->feed_div_min) 168 n = pll->feed_div_min; 169 fvco = (fxtal * (n + 1)) / (m + 1); 170 if (fvco < fwant) 171 diff = fwant - fvco; 172 else 173 diff = fvco - fwant; 174 if (diff < bestdiff) { 175 bestdiff = diff; 176 *post = p; 177 *in = m; 178 *feed = n; 179 bestvco = fvco; 180 } 181 } 182 } 183 dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant); 184 return bestvco; 185} 186 187int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) { 188 unsigned int hd, hs, he, hbe, ht; 189 unsigned int vd, vs, ve, vt, lc; 190 unsigned int wd; 191 unsigned int divider; 192 int i; 193 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw); 194 195 DBG(__FUNCTION__) 196 197 hw->SEQ[0] = 0x00; 198 hw->SEQ[1] = 0x01; /* or 0x09 */ 199 hw->SEQ[2] = 0x0F; /* bitplanes */ 200 hw->SEQ[3] = 0x00; 201 hw->SEQ[4] = 0x0E; 202 /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */ 203 if (m->dblscan) { 204 m->VTotal <<= 1; 205 m->VDisplay <<= 1; 206 m->VSyncStart <<= 1; 207 m->VSyncEnd <<= 1; 208 } 209 if (m->interlaced) { 210 m->VTotal >>= 1; 211 m->VDisplay >>= 1; 212 m->VSyncStart >>= 1; 213 m->VSyncEnd >>= 1; 214 } 215 216 /* GCTL is ignored when not using 0xA0000 aperture */ 217 hw->GCTL[0] = 0x00; 218 hw->GCTL[1] = 0x00; 219 hw->GCTL[2] = 0x00; 220 hw->GCTL[3] = 0x00; 221 hw->GCTL[4] = 0x00; 222 hw->GCTL[5] = 0x40; 223 hw->GCTL[6] = 0x05; 224 hw->GCTL[7] = 0x0F; 225 hw->GCTL[8] = 0xFF; 226 227 /* Whole ATTR is ignored in PowerGraphics mode */ 228 for (i = 0; i < 16; i++) 229 hw->ATTR[i] = i; 230 hw->ATTR[16] = 0x41; 231 hw->ATTR[17] = 0xFF; 232 hw->ATTR[18] = 0x0F; 233 hw->ATTR[19] = 0x00; 234 hw->ATTR[20] = 0x00; 235 236 hd = m->HDisplay >> 3; 237 hs = m->HSyncStart >> 3; 238 he = m->HSyncEnd >> 3; 239 ht = m->HTotal >> 3; 240 /* standard timmings are in 8pixels, but for interleaved we cannot */ 241 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */ 242 /* using 16 or more pixels per unit can save us */ 243 divider = ACCESS_FBINFO(curr.final_bppShift); 244 while (divider & 3) { 245 hd >>= 1; 246 hs >>= 1; 247 he >>= 1; 248 ht >>= 1; 249 divider <<= 1; 250 } 251 divider = divider / 4; 252 /* divider can be from 1 to 8 */ 253 while (divider > 8) { 254 hd <<= 1; 255 hs <<= 1; 256 he <<= 1; 257 ht <<= 1; 258 divider >>= 1; 259 } 260 hd = hd - 1; 261 hs = hs - 1; 262 he = he - 1; 263 ht = ht - 1; 264 vd = m->VDisplay - 1; 265 vs = m->VSyncStart - 1; 266 ve = m->VSyncEnd - 1; 267 vt = m->VTotal - 2; 268 lc = vd; 269 /* G200 cannot work with (ht & 7) == 6 */ 270 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04)) 271 ht++; 272 hbe = ht; 273 wd = ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64; 274 275 hw->CRTCEXT[0] = 0; 276 hw->CRTCEXT[5] = 0; 277 if (m->interlaced) { 278 hw->CRTCEXT[0] = 0x80; 279 hw->CRTCEXT[5] = (hs + he - ht) >> 1; 280 if (!m->dblscan) 281 wd <<= 1; 282 vt &= ~1; 283 } 284 hw->CRTCEXT[0] |= (wd & 0x300) >> 4; 285 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) | 286 ((hd & 0x100) >> 7) | /* blanking */ 287 ((hs & 0x100) >> 6) | /* sync start */ 288 (hbe & 0x040); /* end hor. blanking */ 289 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1) 290 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */ 291 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) | 292 ((vd & 0x400) >> 8) | /* disp end */ 293 ((vd & 0xC00) >> 7) | /* vblanking start */ 294 ((vs & 0xC00) >> 5) | 295 ((lc & 0x400) >> 3); 296 hw->CRTCEXT[3] = (divider - 1) | 0x80; 297 hw->CRTCEXT[4] = 0; 298 299 hw->CRTC[0] = ht-4; 300 hw->CRTC[1] = hd; 301 hw->CRTC[2] = hd; 302 hw->CRTC[3] = (hbe & 0x1F) | 0x80; 303 hw->CRTC[4] = hs; 304 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F); 305 hw->CRTC[6] = vt & 0xFF; 306 hw->CRTC[7] = ((vt & 0x100) >> 8) | 307 ((vd & 0x100) >> 7) | 308 ((vs & 0x100) >> 6) | 309 ((vd & 0x100) >> 5) | 310 ((lc & 0x100) >> 4) | 311 ((vt & 0x200) >> 4) | 312 ((vd & 0x200) >> 3) | 313 ((vs & 0x200) >> 2); 314 hw->CRTC[8] = 0x00; 315 hw->CRTC[9] = ((vd & 0x200) >> 4) | 316 ((lc & 0x200) >> 3); 317 if (m->dblscan && !m->interlaced) 318 hw->CRTC[9] |= 0x80; 319 for (i = 10; i < 16; i++) 320 hw->CRTC[i] = 0x00; 321 hw->CRTC[16] = vs /* & 0xFF */; 322 hw->CRTC[17] = (ve & 0x0F) | 0x20; 323 hw->CRTC[18] = vd /* & 0xFF */; 324 hw->CRTC[19] = wd /* & 0xFF */; 325 hw->CRTC[20] = 0x00; 326 hw->CRTC[21] = vd /* & 0xFF */; 327 hw->CRTC[22] = (vt + 1) /* & 0xFF */; 328 hw->CRTC[23] = 0xC3; 329 hw->CRTC[24] = lc; 330 return 0; 331}; 332 333void matroxfb_vgaHWrestore(WPMINFO2) { 334 int i; 335 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw); 336 CRITFLAGS 337 338 DBG(__FUNCTION__) 339 340 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg); 341 dprintk(KERN_INFO "SEQ regs: "); 342 for (i = 0; i < 5; i++) 343 dprintk("%02X:", hw->SEQ[i]); 344 dprintk("\n"); 345 dprintk(KERN_INFO "GDC regs: "); 346 for (i = 0; i < 9; i++) 347 dprintk("%02X:", hw->GCTL[i]); 348 dprintk("\n"); 349 dprintk(KERN_INFO "CRTC regs: "); 350 for (i = 0; i < 25; i++) 351 dprintk("%02X:", hw->CRTC[i]); 352 dprintk("\n"); 353 dprintk(KERN_INFO "ATTR regs: "); 354 for (i = 0; i < 21; i++) 355 dprintk("%02X:", hw->ATTR[i]); 356 dprintk("\n"); 357 358 CRITBEGIN 359 360 mga_inb(M_ATTR_RESET); 361 mga_outb(M_ATTR_INDEX, 0); 362 mga_outb(M_MISC_REG, hw->MiscOutReg); 363 for (i = 1; i < 5; i++) 364 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]); 365 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F); 366 for (i = 0; i < 25; i++) 367 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]); 368 for (i = 0; i < 9; i++) 369 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]); 370 for (i = 0; i < 21; i++) { 371 mga_inb(M_ATTR_RESET); 372 mga_outb(M_ATTR_INDEX, i); 373 mga_outb(M_ATTR_INDEX, hw->ATTR[i]); 374 } 375 mga_outb(M_PALETTE_MASK, 0xFF); 376 mga_outb(M_DAC_REG, 0x00); 377 for (i = 0; i < 768; i++) 378 mga_outb(M_DAC_VAL, hw->DACpal[i]); 379 mga_inb(M_ATTR_RESET); 380 mga_outb(M_ATTR_INDEX, 0x20); 381 382 CRITEND 383} 384 385static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) { 386 unsigned int b0 = readb(pins); 387 388 if (b0 == 0x2E && readb(pins+1) == 0x41) { 389 unsigned int pins_len = readb(pins+2); 390 unsigned int i; 391 unsigned char cksum; 392 unsigned char* dst = bd->pins; 393 394 if (pins_len < 3 || pins_len > 128) { 395 return; 396 } 397 *dst++ = 0x2E; 398 *dst++ = 0x41; 399 *dst++ = pins_len; 400 cksum = 0x2E + 0x41 + pins_len; 401 for (i = 3; i < pins_len; i++) { 402 cksum += *dst++ = readb(pins+i); 403 } 404 if (cksum) { 405 return; 406 } 407 bd->pins_len = pins_len; 408 } else if (b0 == 0x40 && readb(pins+1) == 0x00) { 409 unsigned int i; 410 unsigned char* dst = bd->pins; 411 412 *dst++ = 0x40; 413 *dst++ = 0; 414 for (i = 2; i < 0x40; i++) { 415 *dst++ = readb(pins+i); 416 } 417 bd->pins_len = 0x40; 418 } 419} 420 421static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) { 422 unsigned int pcir_offset; 423 424 pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8); 425 if (pcir_offset >= 26 && pcir_offset < 0xFFE0 && 426 readb(vbios + pcir_offset ) == 'P' && 427 readb(vbios + pcir_offset + 1) == 'C' && 428 readb(vbios + pcir_offset + 2) == 'I' && 429 readb(vbios + pcir_offset + 3) == 'R') { 430 unsigned char h; 431 432 h = readb(vbios + pcir_offset + 0x12); 433 bd->version.vMaj = (h >> 4) & 0xF; 434 bd->version.vMin = h & 0xF; 435 bd->version.vRev = readb(vbios + pcir_offset + 0x13); 436 } else { 437 unsigned char h; 438 439 h = readb(vbios + 5); 440 bd->version.vMaj = (h >> 4) & 0xF; 441 bd->version.vMin = h & 0xF; 442 bd->version.vRev = 0; 443 } 444} 445 446static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) { 447 unsigned char b; 448 449 b = readb(vbios + 0x7FF1); 450 if (b == 0xFF) { 451 b = 0; 452 } 453 bd->output.state = b; 454} 455 456static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) { 457 unsigned int i; 458 459 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */ 460 bd->output.tvout = 0; 461 if (readb(vbios + 0x1D) != 'I' || 462 readb(vbios + 0x1E) != 'B' || 463 readb(vbios + 0x1F) != 'M' || 464 readb(vbios + 0x20) != ' ') { 465 return; 466 } 467 for (i = 0x2D; i < 0x2D + 128; i++) { 468 unsigned char b = readb(vbios + i); 469 470 if (b == '(' && readb(vbios + i + 1) == 'V') { 471 if (readb(vbios + i + 6) == 'T' && 472 readb(vbios + i + 7) == 'V' && 473 readb(vbios + i + 8) == 'O') { 474 bd->output.tvout = 1; 475 } 476 return; 477 } 478 if (b == 0) 479 break; 480 } 481} 482 483static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) { 484 unsigned int pins_offset; 485 486 if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) { 487 return; 488 } 489 bd->bios_valid = 1; 490 get_bios_version(vbios, bd); 491 get_bios_output(vbios, bd); 492 get_bios_tvout(vbios, bd); 493#if defined(__powerpc__) 494 /* On PowerPC cards, the PInS offset isn't stored at the end of the 495 * BIOS image. Instead, you must search the entire BIOS image for 496 * the magic PInS signature. 497 * 498 * This actually applies to all OpenFirmware base cards. Since these 499 * cards could be put in a MIPS or SPARC system, should the condition 500 * be something different? 501 */ 502 for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) { 503 unsigned char header[3]; 504 505 header[0] = readb(vbios + pins_offset); 506 header[1] = readb(vbios + pins_offset + 1); 507 header[2] = readb(vbios + pins_offset + 2); 508 if ( (header[0] == 0x2E) && (header[1] == 0x41) 509 && ((header[2] == 0x40) || (header[2] == 0x80)) ) { 510 printk(KERN_INFO "PInS data found at offset %u\n", 511 pins_offset); 512 get_pins(vbios + pins_offset, bd); 513 break; 514 } 515 } 516#else 517 pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8); 518 if (pins_offset <= 0xFF80) { 519 get_pins(vbios + pins_offset, bd); 520 } 521#endif 522} 523 524#define get_u16(x) (le16_to_cpu(get_unaligned((__u16*)(x)))) 525#define get_u32(x) (le32_to_cpu(get_unaligned((__u32*)(x)))) 526static int parse_pins1(WPMINFO const struct matrox_bios* bd) { 527 unsigned int maxdac; 528 529 switch (bd->pins[22]) { 530 case 0: maxdac = 175000; break; 531 case 1: maxdac = 220000; break; 532 default: maxdac = 240000; break; 533 } 534 if (get_u16(bd->pins + 24)) { 535 maxdac = get_u16(bd->pins + 24) * 10; 536 } 537 MINFO->limits.pixel.vcomax = maxdac; 538 MINFO->values.pll.system = get_u16(bd->pins + 28) ? get_u16(bd->pins + 28) * 10 : 50000; 539 /* ignore 4MB, 8MB, module clocks */ 540 MINFO->features.pll.ref_freq = 14318; 541 MINFO->values.reg.mctlwtst = 0x00030101; 542 return 0; 543} 544 545static void default_pins1(WPMINFO2) { 546 /* Millennium */ 547 MINFO->limits.pixel.vcomax = 220000; 548 MINFO->values.pll.system = 50000; 549 MINFO->features.pll.ref_freq = 14318; 550 MINFO->values.reg.mctlwtst = 0x00030101; 551} 552 553static int parse_pins2(WPMINFO const struct matrox_bios* bd) { 554 MINFO->limits.pixel.vcomax = 555 MINFO->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000); 556 MINFO->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) | 557 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) | 558 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) | 559 ((bd->pins[51] & 0x08) ? 0x00020000 : 0); 560 MINFO->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000); 561 MINFO->features.pll.ref_freq = 14318; 562 return 0; 563} 564 565static void default_pins2(WPMINFO2) { 566 /* Millennium II, Mystique */ 567 MINFO->limits.pixel.vcomax = 568 MINFO->limits.system.vcomax = 230000; 569 MINFO->values.reg.mctlwtst = 0x00030101; 570 MINFO->values.pll.system = 50000; 571 MINFO->features.pll.ref_freq = 14318; 572} 573 574static int parse_pins3(WPMINFO const struct matrox_bios* bd) { 575 MINFO->limits.pixel.vcomax = 576 MINFO->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000); 577 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 48) == 0xFFFFFFFF ? 0x01250A21 : get_u32(bd->pins + 48); 578 /* memory config */ 579 MINFO->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) | 580 ((bd->pins[57] << 22) & 0x00C00000) | 581 ((bd->pins[56] << 1) & 0x000001E0) | 582 ( bd->pins[56] & 0x0000000F); 583 MINFO->values.reg.opt = (bd->pins[54] & 7) << 10; 584 MINFO->values.reg.opt2 = bd->pins[58] << 12; 585 MINFO->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; 586 return 0; 587} 588 589static void default_pins3(WPMINFO2) { 590 /* G100, G200 */ 591 MINFO->limits.pixel.vcomax = 592 MINFO->limits.system.vcomax = 230000; 593 MINFO->values.reg.mctlwtst = 0x01250A21; 594 MINFO->values.reg.memrdbk = 0x00000000; 595 MINFO->values.reg.opt = 0x00000C00; 596 MINFO->values.reg.opt2 = 0x00000000; 597 MINFO->features.pll.ref_freq = 27000; 598} 599 600static int parse_pins4(WPMINFO const struct matrox_bios* bd) { 601 MINFO->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000; 602 MINFO->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 38] * 4000; 603 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 71); 604 MINFO->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) | 605 ((bd->pins[87] << 22) & 0x00C00000) | 606 ((bd->pins[86] << 1) & 0x000001E0) | 607 ( bd->pins[86] & 0x0000000F); 608 MINFO->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) | 609 ((bd->pins[53] << 22) & 0x10000000) | 610 ((bd->pins[53] << 7) & 0x00001C00); 611 MINFO->values.reg.opt3 = get_u32(bd->pins + 67); 612 MINFO->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000; 613 MINFO->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; 614 return 0; 615} 616 617static void default_pins4(WPMINFO2) { 618 /* G400 */ 619 MINFO->limits.pixel.vcomax = 620 MINFO->limits.system.vcomax = 252000; 621 MINFO->values.reg.mctlwtst = 0x04A450A1; 622 MINFO->values.reg.memrdbk = 0x000000E7; 623 MINFO->values.reg.opt = 0x10000400; 624 MINFO->values.reg.opt3 = 0x0190A419; 625 MINFO->values.pll.system = 200000; 626 MINFO->features.pll.ref_freq = 27000; 627} 628 629static int parse_pins5(WPMINFO const struct matrox_bios* bd) { 630 unsigned int mult; 631 632 mult = bd->pins[4]?8000:6000; 633 634 MINFO->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult; 635 MINFO->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 36] * mult; 636 MINFO->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax : bd->pins[ 37] * mult; 637 MINFO->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult; 638 MINFO->limits.system.vcomin = (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin : bd->pins[121] * mult; 639 MINFO->limits.video.vcomin = (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin : bd->pins[122] * mult; 640 MINFO->values.pll.system = 641 MINFO->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000; 642 MINFO->values.reg.opt = get_u32(bd->pins+ 48); 643 MINFO->values.reg.opt2 = get_u32(bd->pins+ 52); 644 MINFO->values.reg.opt3 = get_u32(bd->pins+ 94); 645 MINFO->values.reg.mctlwtst = get_u32(bd->pins+ 98); 646 MINFO->values.reg.memmisc = get_u32(bd->pins+102); 647 MINFO->values.reg.memrdbk = get_u32(bd->pins+106); 648 MINFO->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000; 649 MINFO->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; 650 MINFO->values.memory.dll = (bd->pins[115] & 0x02) != 0; 651 MINFO->values.memory.emrswen = (bd->pins[115] & 0x01) != 0; 652 MINFO->values.reg.maccess = MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000; 653 if (bd->pins[115] & 4) { 654 MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst; 655 } else { 656 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 }; 657 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) | 658 wtst_xlat[MINFO->values.reg.mctlwtst & 7]; 659 } 660 return 0; 661} 662 663static void default_pins5(WPMINFO2) { 664 /* Mine 16MB G450 with SDRAM DDR */ 665 MINFO->limits.pixel.vcomax = 666 MINFO->limits.system.vcomax = 667 MINFO->limits.video.vcomax = 600000; 668 MINFO->limits.pixel.vcomin = 669 MINFO->limits.system.vcomin = 670 MINFO->limits.video.vcomin = 256000; 671 MINFO->values.pll.system = 672 MINFO->values.pll.video = 284000; 673 MINFO->values.reg.opt = 0x404A1160; 674 MINFO->values.reg.opt2 = 0x0000AC00; 675 MINFO->values.reg.opt3 = 0x0090A409; 676 MINFO->values.reg.mctlwtst_core = 677 MINFO->values.reg.mctlwtst = 0x0C81462B; 678 MINFO->values.reg.memmisc = 0x80000004; 679 MINFO->values.reg.memrdbk = 0x01001103; 680 MINFO->features.pll.ref_freq = 27000; 681 MINFO->values.memory.ddr = 1; 682 MINFO->values.memory.dll = 1; 683 MINFO->values.memory.emrswen = 1; 684 MINFO->values.reg.maccess = 0x00004000; 685} 686 687static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) { 688 unsigned int pins_version; 689 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 }; 690 691 switch (ACCESS_FBINFO(chip)) { 692 case MGA_2064: default_pins1(PMINFO2); break; 693 case MGA_2164: 694 case MGA_1064: 695 case MGA_1164: default_pins2(PMINFO2); break; 696 case MGA_G100: 697 case MGA_G200: default_pins3(PMINFO2); break; 698 case MGA_G400: default_pins4(PMINFO2); break; 699 case MGA_G450: 700 case MGA_G550: default_pins5(PMINFO2); break; 701 } 702 if (!bd->bios_valid) { 703 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n"); 704 return -1; 705 } 706 if (bd->pins_len < 64) { 707 printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n"); 708 return -1; 709 } 710 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) { 711 pins_version = bd->pins[5]; 712 if (pins_version < 2 || pins_version > 5) { 713 printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version); 714 return -1; 715 } 716 } else { 717 pins_version = 1; 718 } 719 if (bd->pins_len != pinslen[pins_version - 1]) { 720 printk(KERN_INFO "matroxfb: Invalid powerup info\n"); 721 return -1; 722 } 723 switch (pins_version) { 724 case 1: 725 return parse_pins1(PMINFO bd); 726 case 2: 727 return parse_pins2(PMINFO bd); 728 case 3: 729 return parse_pins3(PMINFO bd); 730 case 4: 731 return parse_pins4(PMINFO bd); 732 case 5: 733 return parse_pins5(PMINFO bd); 734 default: 735 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version); 736 return -1; 737 } 738} 739 740void matroxfb_read_pins(WPMINFO2) { 741 u32 opt; 742 u32 biosbase; 743 u32 fbbase; 744 struct pci_dev* pdev = ACCESS_FBINFO(pcidev); 745 746 memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios))); 747 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt); 748 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM); 749 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase); 750 pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase); 751 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE); 752 parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios)); 753 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase); 754 pci_write_config_dword(pdev, PCI_OPTION_REG, opt); 755#ifdef CONFIG_X86 756 if (!ACCESS_FBINFO(bios).bios_valid) { 757 unsigned char __iomem* b; 758 759 b = ioremap(0x000C0000, 65536); 760 if (!b) { 761 printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n"); 762 } else { 763 unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8); 764 unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8); 765 766 if (ven != pdev->vendor || dev != pdev->device) { 767 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n", 768 ven, dev, pdev->vendor, pdev->device); 769 } else { 770 parse_bios(b, &ACCESS_FBINFO(bios)); 771 } 772 iounmap(b); 773 } 774 } 775#endif 776 matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios)); 777 printk(KERN_INFO "PInS memtype = %u\n", 778 (ACCESS_FBINFO(values).reg.opt & 0x1C00) >> 10); 779} 780 781EXPORT_SYMBOL(matroxfb_DAC_in); 782EXPORT_SYMBOL(matroxfb_DAC_out); 783EXPORT_SYMBOL(matroxfb_var2my); 784EXPORT_SYMBOL(matroxfb_PLL_calcclock); 785#ifndef CONFIG_FB_MATROX_MULTIHEAD 786struct matrox_fb_info matroxfb_global_mxinfo; 787EXPORT_SYMBOL(matroxfb_global_mxinfo); 788#endif 789EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */ 790EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */ 791EXPORT_SYMBOL(matroxfb_read_pins); 792 793MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>"); 794MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards"); 795MODULE_LICENSE("GPL"); 796