/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/isdn/hisax/ |
H A D | avm_a1p.c | 67 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset); 68 ret = bytein(cs->hw.avm.cfg_reg+DATAREG_OFFSET); 76 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_REG_OFFSET+offset); 77 byteout(cs->hw.avm.cfg_reg+DATAREG_OFFSET, value); 83 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET); 84 insb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size); 90 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET,ISAC_FIFO_OFFSET); 91 outsb(cs->hw.avm.cfg_reg+DATAREG_OFFSET, data, size); 100 byteout(cs->hw.avm.cfg_reg+ADDRREG_OFFSET, 102 ret = bytein(cs->hw.avm.cfg_reg [all...] |
H A D | teles3.c | 163 if (cs->hw.teles3.cfg_reg) { 165 release_region(cs->hw.teles3.cfg_reg, 1); 167 release_region(cs->hw.teles3.cfg_reg, 8); 180 if ((cs->hw.teles3.cfg_reg) && (cs->typ != ISDN_CTYPE_COMPAQ_ISA)) { 210 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg); 212 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1); 215 byteout(cs->hw.teles3.cfg_reg, 0xff); 217 byteout(cs->hw.teles3.cfg_reg, 0x00); 332 cs->hw.teles3.cfg_reg = card->para[1]; 333 switch (cs->hw.teles3.cfg_reg) { [all...] |
H A D | s0box.c | 99 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset)); 105 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); 111 read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); 117 write_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.isacfifo, data, size); 123 return (readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset)); 129 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); 136 #define READHSCX(cs, nr, reg) readreg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg) 137 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, data) 138 #define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscxfifo[nr], ptr, cnt) 139 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo(cs->hw.teles3.cfg_reg, c [all...] |
H A D | avm_a1.c | 111 while (((sval = bytein(cs->hw.avm.cfg_reg)) & 0xf) != 0x7) { 113 byteout(cs->hw.avm.cfg_reg, 0x1E); 114 sval = bytein(cs->hw.avm.cfg_reg); 141 release_region(cs->hw.avm.cfg_reg, 8); 170 byteout(cs->hw.avm.cfg_reg, 0x16); 171 byteout(cs->hw.avm.cfg_reg, 0x1E); 193 cs->hw.avm.cfg_reg = card->para[1] + 0x1800; 201 if (!request_region(cs->hw.avm.cfg_reg, 8, "avm cfg")) { 205 cs->hw.avm.cfg_reg, 206 cs->hw.avm.cfg_reg [all...] |
H A D | teles0.c | 189 if (cs->hw.teles0.cfg_reg) 190 release_region(cs->hw.teles0.cfg_reg, 8); 200 if (cs->hw.teles0.cfg_reg) { 231 byteout(cs->hw.teles0.cfg_reg + 4, cfval); 233 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1); 281 cs->hw.teles0.cfg_reg = card->para[2]; 283 cs->hw.teles0.cfg_reg = 0; 292 if (cs->hw.teles0.cfg_reg) { 293 if (!request_region(cs->hw.teles0.cfg_reg, 8, "teles cfg")) { 297 cs->hw.teles0.cfg_reg, [all...] |
H A D | sportster.c | 130 bytein(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ +1); 140 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0); 142 adr = cs->hw.spt.cfg_reg + i *1024; 151 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); 154 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); 177 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); 193 adr = cs->hw.spt.cfg_reg + i *1024; 205 adr = cs->hw.spt.cfg_reg + j *1024; 223 cs->hw.spt.cfg_reg = card->para[1]; 227 cs->hw.spt.isac = cs->hw.spt.cfg_reg [all...] |
H A D | sedlbauer.c | 406 if (cs->hw.sedl.cfg_reg) 407 release_region(cs->hw.sedl.cfg_reg, bytecnt); 429 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_on); 431 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off); 497 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off); 508 byteout(cs->hw.sedl.cfg_reg +3, cs->hw.sedl.reset_off); 560 cs->hw.sedl.cfg_reg = card->para[1]; 595 cs->hw.sedl.cfg_reg = card->para[1]; 630 cs->hw.sedl.cfg_reg = pci_resource_start(dev_sedl, 0); 642 cs->hw.sedl.cfg_reg); [all...] |
H A D | avm_pci.c | 83 outb(idx, cs->hw.avm.cfg_reg + 4); 93 outb(idx, cs->hw.avm.cfg_reg + 4); 100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); 107 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); 117 outl(idx, cs->hw.avm.cfg_reg + 4); 127 outl(idx, cs->hw.avm.cfg_reg + 4); 137 outb(idx, cs->hw.avm.cfg_reg + 4); 147 outb(idx, cs->hw.avm.cfg_reg + 4); 264 outl(idx, cs->hw.avm.cfg_reg + 4); 278 outb(idx, cs->hw.avm.cfg_reg [all...] |
H A D | mic.c | 165 if (cs->hw.mic.cfg_reg) 166 release_region(cs->hw.mic.cfg_reg, bytecnt); 205 cs->hw.mic.cfg_reg = card->para[1]; 207 cs->hw.mic.adr = cs->hw.mic.cfg_reg + MIC_ADR; 208 cs->hw.mic.isac = cs->hw.mic.cfg_reg + MIC_ISAC; 209 cs->hw.mic.hscx = cs->hw.mic.cfg_reg + MIC_HSCX; 211 if (!request_region(cs->hw.mic.cfg_reg, bytecnt, "mic isdn")) { 215 cs->hw.mic.cfg_reg, 216 cs->hw.mic.cfg_reg + bytecnt); 220 cs->hw.mic.cfg_reg, c [all...] |
H A D | niccy.c | 134 ival = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 139 outl(ival, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 179 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 181 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 182 release_region(cs->hw.niccy.cfg_reg, 0x40); 195 val = inl(cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 197 outl(val, cs->hw.niccy.cfg_reg + PCI_IRQ_CTRL_REG); 284 cs->hw.niccy.cfg_reg = 0; 317 cs->hw.niccy.cfg_reg = pci_resource_start(niccy_dev, 0); 318 if (!cs->hw.niccy.cfg_reg) { [all...] |
H A D | saphir.c | 177 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff); 180 if (cs->hw.saphir.cfg_reg) 181 release_region(cs->hw.saphir.cfg_reg, 6); 208 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); 209 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1); 211 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 0); 213 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); 214 byteout(cs->hw.saphir.cfg_reg + SPARE_REG, 0x02); 256 cs->hw.saphir.cfg_reg = card->para[1]; 261 if (!request_region(cs->hw.saphir.cfg_reg, [all...] |
H A D | diva.c | 198 return (memreadreg(cs->hw.diva.cfg_reg, offset+0x80)); 204 memwritereg(cs->hw.diva.cfg_reg, offset|0x80, value); 211 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0x80); 218 memwritereg(cs->hw.diva.cfg_reg, 0x80, *data++); 224 return(memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0))); 230 memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value); 237 return (memreadreg(cs->hw.diva.cfg_reg, offset)); 243 memwritereg(cs->hw.diva.cfg_reg, offset, value); 250 *data++ = memreadreg(cs->hw.diva.cfg_reg, 0); 257 memwritereg(cs->hw.diva.cfg_reg, [all...] |
H A D | asuscom.c | 247 if (cs->hw.asus.cfg_reg) 248 release_region(cs->hw.asus.cfg_reg, bytecnt); 375 cs->hw.asus.cfg_reg = card->para[1]; 377 if (!request_region(cs->hw.asus.cfg_reg, bytecnt, "asuscom isdn")) { 381 cs->hw.asus.cfg_reg, 382 cs->hw.asus.cfg_reg + bytecnt); 386 cs->hw.asus.cfg_reg, cs->irq); 392 val = readreg(cs->hw.asus.cfg_reg + ASUS_IPAC_ALE, 393 cs->hw.asus.cfg_reg + ASUS_IPAC_DATA, IPAC_ID); 396 cs->hw.asus.adr = cs->hw.asus.cfg_reg [all...] |
H A D | ix1_micro.c | 168 if (cs->hw.ix1.cfg_reg) 169 release_region(cs->hw.ix1.cfg_reg, 4); 180 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1); 183 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0); 286 cs->hw.ix1.cfg_reg = card->para[1]; 288 if (cs->hw.ix1.cfg_reg) { 289 if (!request_region(cs->hw.ix1.cfg_reg, 4, "ix1micro cfg")) { 293 cs->hw.ix1.cfg_reg, 294 cs->hw.ix1.cfg_reg + 4); 299 CardType[cs->typ], cs->irq, cs->hw.ix1.cfg_reg); [all...] |
H A D | hisax.h | 572 unsigned int cfg_reg; member in struct:teles3_hw 580 unsigned int cfg_reg; member in struct:teles0_hw 586 unsigned int cfg_reg; member in struct:avm_hw 596 unsigned int cfg_reg; member in struct:ix1_hw 604 unsigned long cfg_reg; member in struct:diva_hw 618 unsigned int cfg_reg; member in struct:asus_hw 638 unsigned int cfg_reg; member in struct:sedl_hw 651 unsigned int cfg_reg; member in struct:spt_hw 658 unsigned int cfg_reg; member in struct:mic_hw 759 unsigned int cfg_reg; member in struct:saphir_hw 781 unsigned int cfg_reg; member in struct:gazel_hw [all...] |
H A D | gazel.c | 334 release_region(cs->hw.gazel.cfg_reg, 0x80); 339 release_region(cs->hw.gazel.cfg_reg, 0x80); 351 unsigned long plxcntrl, addr = cs->hw.gazel.cfg_reg; 458 if (!request_region(adr = cs->hw.gazel.cfg_reg, len = 0x80, "gazel")) { 467 if (!request_region(adr = cs->hw.gazel.cfg_reg, len = 0x80, "gazel")) { 501 cs->hw.gazel.cfg_reg = card->para[1] + 0xC000; 517 cs->irq, cs->hw.gazel.isac, cs->hw.gazel.cfg_reg); 586 cs->hw.gazel.cfg_reg = pci_ioaddr0 & 0xfffe; 604 cs->irq, cs->hw.gazel.isac, cs->hw.gazel.cfg_reg); 617 cs->irq, cs->hw.gazel.ipac, cs->hw.gazel.cfg_reg); [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/sparc64/kernel/ |
H A D | sbus.c | 578 unsigned long cfg_reg; local 581 cfg_reg = iommu->write_complete_reg; 584 cfg_reg += 0x20UL; 587 cfg_reg += 0x28UL; 590 cfg_reg += 0x30UL; 593 cfg_reg += 0x38UL; 596 cfg_reg += 0x40UL; 599 cfg_reg += 0x48UL; 602 cfg_reg += 0x50UL; 609 val = upa_readq(cfg_reg); [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/scsi/ |
H A D | gdth.h | 786 unchar cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/ member in struct:__anon6545
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