Searched refs:cache_line_size (Results 1 - 13 of 13) sorted by relevance
| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/pci/hotplug/ |
| H A D | shpchp_pci.c | 57 hpp.t0->cache_line_size = 8;
64 PCI_CACHE_LINE_SIZE, hpp.t0->cache_line_size);
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| H A D | acpi_pcihp.c | 66 hpx->t0->cache_line_size = fields[2].integer.value;
280 hpp->t0->cache_line_size = nui[0];
285 pr_debug(" _HPP: cache_line_size=0x%x\n", hpp->t0->cache_line_size);
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| H A D | pciehp_pci.c | 47 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
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| H A D | acpiphp_glue.c | 359 bridge->hpp.t0->cache_line_size = 0x10;
1372 bridge->hpp.t0->cache_line_size);
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| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/linux/ |
| H A D | pci_hotplug.h | 182 u8 cache_line_size; member in struct:hpp_type0
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| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/include/ |
| H A D | pcicfg.h | 120 uint8 cache_line_size; member in struct:_pci_config_regs
368 uint8 cache_line_size; member in struct:_ppb_config_regs
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| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-x86_64/ |
| H A D | processor.h | 444 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) macro
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| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-i386/ |
| H A D | processor.h | 746 #define cache_line_size() (boot_cpu_data.x86_cache_alignment) macro
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| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/mm/ |
| H A D | slab.c | 142 #ifndef cache_line_size
143 #define cache_line_size() L1_CACHE_BYTES macro
149 * Usually, the kmalloc caches are cache_line_size() aligned, except when
1433 cache_cache.colour_off = cache_line_size();
1447 cache_line_size());
1453 cache_line_size(), 0, &left_over, &cache_cache.num);
1461 sizeof(struct slab), cache_line_size());
2209 ralign = cache_line_size();
2277 && cachep->obj_size > cache_line_size() && size < PAGE_SIZE) {
2325 cachep->colour_off = cache_line_size();
[all...] |
| H A D | slub.c | 211 /* Not all arches define cache_line_size */
212 #ifndef cache_line_size
213 #define cache_line_size() L1_CACHE_BYTES macro
1765 size > cache_line_size() / 2)
1766 return max_t(unsigned long, align, cache_line_size());
2493 caches, cache_line_size(),
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| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/block/ |
| H A D | cpqarray.c | 608 unchar cache_line_size, latency_timer; local
635 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
655 printk("cache_line_size = %x\n", cache_line_size);
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| /netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/scsi/ |
| H A D | ipr.h | 1021 u8 cache_line_size; member in struct:ipr_chip_cfg_t
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| H A D | ipr.c | 102 .cache_line_size = 0x20,
117 .cache_line_size = 0x20,
7570 ioa_cfg->chip_cfg->cache_line_size);
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