Searched refs:ZS_CLOCK (Results 1 - 5 of 5) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/serial/
H A Dsunzilog.c70 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */ macro
292 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
955 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1191 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1255 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1334 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1390 up[0].port.uartclk = ZS_CLOCK;
1407 up[1].port.uartclk = ZS_CLOCK;
H A Dip22zilog.c61 #define ZS_CLOCK 3672000 /* Zilog input clock rate. */ macro
853 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1051 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1125 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1136 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1173 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
H A Dpmac_zilog.h116 #define ZS_CLOCK 3686400 /* Z8530 RTxC input clock rate */ macro
H A Dpmac_zilog.c1025 case ZS_CLOCK/16: /* 230400 */
1030 case ZS_CLOCK/32: /* 115200 */
1038 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1469 uap->port.uartclk = ZS_CLOCK;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/tc/
H A Dzs.c93 #define ZS_CLOCK 7372800 /* Z8530 RTxC input clock rate */ macro
117 clock : ZS_CLOCK

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