Searched refs:TWI_CLKDIV (Results 1 - 4 of 4) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h879 #define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
880 #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
H A DdefBF52x_base.h483 #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ macro
1496 /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h860 #define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
861 #define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val)
H A DdefBF534.h459 #define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ macro
1753 /* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */

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