Searched refs:SPORT0_TCLKDIV (Results 1 - 12 of 12) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A DcdefBF532.h594 #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
595 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
H A DdefBF532.h156 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h297 #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
298 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
H A DdefBF52x_base.h183 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf548/
H A DdefBF548.h69 #define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ macro
H A DcdefBF548.h89 #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
H A DcdefBF549.h89 #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
H A DdefBF549.h70 #define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A DdefBF561.h257 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ macro
H A DcdefBF561.h434 #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
435 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h282 #define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
283 #define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV,val)
H A DdefBF534.h164 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ macro

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