Searched refs:R5 (Results 1 - 25 of 37) sorted by relevance

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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/bfin/
H A Dvp3_idct_bfin.S127 * R5 = (Y1,Y7)
132 A1=R7.L*R1.H, A0=R7.H*R1.H (IS) || I0+=4 || R5.H=W[I0];
133 R1=(A1-=R7.H*R1.L), R0=(A0+=R7.L*R1.L) (IS) || R5.L=W[I1--] || R7=[I3++];
153 // R5=(Y1,Y7) R6=(Y5,Y3) // R7=(C1,C7)
154 A1 =R7.L*R5.H, A0 =R7.H*R5.H (IS) || [TMP1]=R2 || R6.H=W[I2--];
155 A1-=R7.H*R5.L, A0+=R7.L*R5.L (IS) || I0-=4 || R7=[I3++];
158 A1 =R7.L*R5.H, A0 =R7.H*R5
[all...]
H A Didct_bfin.S154 * R5 = (Y1,Y7)
159 A1=R7.L*R1.H, A0=R7.H*R1.H (IS) || I0+=4 || R5.H=W[I0];
160 R1=(A1-=R7.H*R1.L), R0=(A0+=R7.L*R1.L) (IS) || R5.L=W[I1--] || R7=[I3++];
180 // R5=(Y1,Y7) R6=(Y5,Y3) // R7=(C1,C7)
181 A1 =R7.L*R5.H, A0 =R7.H*R5.H (IS) || [TMP1]=R2 || R6.H=W[I2--];
182 A1-=R7.H*R5.L, A0+=R7.L*R5.L (IS) || I0-=4 || R7=[I3++];
185 A1 =R7.L*R5.H, A0 =R7.H*R5
[all...]
H A Dpixels_bfin.S27 R5.l = 0x00ff;
28 R5.h = 0x00ff;
38 ppc$0: R2 = MIN(R2, R5) (V);
40 R3 = MIN(R3, R5) (V) || R0 = [I0++];
43 R2 = MIN(R2, R5) (V);
45 R3 = MIN(R3, R5) (V) || R0 = [I0++];
253 R5 = BYTEOP2P (R3:2,R1:0) (RNDL,R) || R1 = [I0++] || [I3++] = R4 ; define
254 DISALGNEXCPT || R3 = [I1++] || [I3++] = R5;
256 R5 = BYTEOP2P (R3:2,R1:0) (RNDL,R) || R0 = [I0++] || [I3++] = R4 ; define
257 LE$16E: DISALGNEXCPT || R2 = [I1++] || [I3++M2] = R5;
271 R5 = BYTEOP2P (R3:2,R1:0) (RNDH,R) || R1 = [I0++] || R6 =[I3++]; define
273 R5 = R5 +|+ R7 || [I3++] = R4; define
276 R5 = BYTEOP2P (R3:2,R1:0) (RNDH,R) || R0 = [I0++] || R6 = [I3++]; define
278 R5 = R5 +|+ R7 || [I3++] = R4; define
311 R5 = BYTEOP2P (R3:2,R1:0) (TL,R) || R1 = [I0++] || [I3++] = R4 ; define
314 R5 = BYTEOP2P (R3:2,R1:0) (TL,R) || R0 = [I0++] || [I3++] = R4 ; define
329 R5 = BYTEOP2P (R3:2,R1:0) (TH,R) || R1 = [I0++] || R6 =[I3++]; define
331 R5 = R5 +|+ R7 || [I3++] = R4; define
334 R5 = BYTEOP2P (R3:2,R1:0) (TH,R) || R0 = [I0++] || R6 = [I3++]; define
336 R5 = R5 +|+ R7 || [I3++] = R4; define
369 R5 = BYTEOP2P (R3:2,R1:0) (RNDL,R) || R0 = [I0++] || [I3++] = R4 ; define
384 R5 = BYTEOP2P (R3:2,R1:0) (RNDH,R) || R0 = [I0++] || R6 =[I3++]; define
386 R5 = R5 +|+ R7 || [I3++] = R4; define
419 R5 = BYTEOP2P (R3:2,R1:0) (TL,R) || R0 = [I0++] || [I3++] = R4 ; define
435 R5 = BYTEOP2P (R3:2,R1:0) (TH,R) || R0 = [I0++] || R6 = [I3++]; define
437 R5 = R5 +|+ R7 || [I3++] = R4; define
[all...]
H A Dfdct_bfin.S60 R0, R1, R2, R3, R4, R5, R6,R7, P0, P1, P2, P3, P4, P5, A0, A1.
70 R6, R5, R4 if modified should be stored and restored.
274 R5.H=(A1-=R0.H*R7.h),R5.L=(A0+=R0.H*R7.h) || R7=[I3++] || NOP;
288 A1=R1.H*R7.L, A0=R1.L*R7.L || W[P0++P3]=R5.L || R2.L=W[I0];
292 /* R2 = (X4, X7) R4 = (X5,X6) R5 = (X1, X0) R6 = (X2,X3). */
302 R2.H=(A1+=R2.L*R7.H),R2.L=(A0-=R2.H*R7.H) || W[P0++P3]=R5.H || R7=[I3++];
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/lib/
H A Ddivsi3.S131 [--SP] = (R7:5); /* Push registers R5-R7 */
136 R5 = R6 >> 31; /* Shift sign to LSB */ define
139 R2 = R2 | R5; /* Shift quotient bit */
145 R0 = R0 << 1 || R5 = [SP];
149 IF CC R5 = R1; /* or we might be adding divisor (AQ==1)*/
150 R0 = R0 + R5; /* do add or subtract, as indicated by AQ */
152 R5 = R6 >> 31; define
154 BITTGL(R5,0); /* tweak AQ to be what we want to shift in */
155 .Llend: R2 = R2 + R5; /* and then set shifted-in value to
H A Dudivsi3.S139 [--SP] = (R7:5); /* Push registers R5-R7 */
175 R3 = R3 << 1 || R5 = [SP];
179 IF CC R5 = R1; /* and if AQ==1, we'll add it. */
180 R3 = R3 + R5; /* Add/sub divsor to partial remainder */
183 R5 = R7 >> 31; /* Get AQ */ define
184 BITTGL(R5, 0); /* Invert it, to get what we'll shift */
185 .Lulend: R2 = R2 + R5; /* and "shift" it in. */
196 R5 = R0 - R3; /* Z = (dividend - Q * divisor) */ define
197 CC = R1 <= R5 (IU); /* Check if divisor <= Z? */
202 (R7:5) = [SP++]; /* Pop registers R5
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-common/
H A Dcplbmgr.S92 R5 = 0; define
112 R5 += 1;
113 CC = BITTST(R5, 4); /* i.e CC = R5 >= 16*/
129 R5 = [P4]; /* Control Register*/ define
130 BITCLR(R5,ENICPLB_P);
134 [P4] = R5;
256 /* P4 points to IMEM_CONTROL, and R5 contains its old
260 BITSET(R5,ENICPLB_P);
264 [P4] = R5;
299 R5 = [P4]; define
335 R5 = CC; define
373 R5 = [P4]; define
[all...]
H A Dlock.S82 R5 = R7; define
100 R7 = R5;
118 R7 = R5;
136 R7 = R5;
H A Ddpmc.S302 R5 = W[P0](z); define
359 w[p0] = R5;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/x86_64/crypto/
H A Daes-x86_64-asm.S42 #define R5 %rsi define
136 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
138 #define return epilogue(R8,R2,R9,R7,R5,R6,R3,R4,R11)
141 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
142 move_regs(R1,R2,R5,R6)
145 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
148 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/serial/
H A Dpmac_zilog.c146 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
176 /* Rewrite R3/R5, this time without enables masked. */
178 write_zsreg(uap, R5, regs[R5]);
567 uap->curregs[R5] |= set_bits;
568 uap->curregs[R5] &= ~clear_bits;
571 write_zsreg(uap, R5, uap->curregs[R5]);
573 set_bits, clear_bits, uap->curregs[R5]);
[all...]
H A Dsunzilog.c211 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
256 /* Rewrite R3/R5, this time without enables masked. */
258 write_zsreg(channel, R5, regs[R5]);
671 up->curregs[R5] |= set_bits;
672 up->curregs[R5] &= ~clear_bits;
673 write_zsreg(channel, R5, up->curregs[R5]);
775 new_reg = (up->curregs[R5] | set_bit
[all...]
H A Dip22zilog.c196 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
227 /* Rewrite R3/R5, this time without enables masked. */
229 write_zsreg(channel, R5, regs[R5]);
569 up->curregs[R5] |= set_bits;
570 up->curregs[R5] &= ~clear_bits;
571 write_zsreg(channel, R5, up->curregs[R5]);
673 new_reg = (up->curregs[R5] | set_bit
[all...]
H A Dip22zilog.h43 #define R5 5 macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/arm/
H A Dsimple_idct_arm.S91 @@ R3=ROWr32[2], R4=ROWr32[3], R5-R11 free
92 orr r5, r4, r3 @ R5=R4 | R3
93 orr r5, r5, r2 @ R5=R4 | R3 | R2
94 orrs r6, r5, r1 @ Test R5 | R1 (the aim is to check if everything is null)
98 orrs r5, r5, r7 @ R5=R4 | R3 | R2 | R7
103 @@ R5=(temp), R6=ROWr16[0], R7=ROWr16[1], R8-R11 free,
122 mul r5, r10, r7 @ R5=W5*ROWr16[1]=b2 (ROWr16[1] must be the second arg, to have the possibility to save 1 cycle)
128 mlane r5, r8, r2, r5 @ R5-=W1*ROWr16[3]=b2 (ROWr16[3] must be the second arg, to have the possibility to save 1 cycle)
132 @@ R5=b2, R6=ROWr16[0], R7=b3, R8=W1, R9=W3, R10=W5, R11=W7,
140 @@ R5
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/media/video/
H A Dwm8739.c52 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator in enum:__anon5079
300 wm8739_write(client, R5, 0x000); /* filter setting, high path, offet clear */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/hamradio/
H A Dscc.c801 wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */
933 or(scc,R5, TxENAB);
934 scc->wreg[R5] |= RTS;
936 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */
939 cl(scc,R5,RTS|TxENAB);
967 or(scc,R5, TxENAB);
968 scc->wreg[R5] |= RTS;
970 or(scc,R5,RTS|TxENAB); /* enable tx */
973 cl(scc,R5,RTS|TxENAB); /* disable tx */
1104 if ( (grp1 & TXGROUP) && (scc2->wreg[R5]
[all...]
H A Dz8530.h11 #define R5 5 macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/sh/kernel/
H A Dkgdb_stub.c140 R0 = 0, R1, R2, R3, R4, R5, R6, R7, enumerator in enum:regs
494 gdb_regs[R5] = regs->regs[R5];
523 regs->regs[R5] = gdb_regs[R5];
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m32r/kernel/
H A Dentry.S84 #define R5(reg) @(0x04,reg) define
252 ld r5, R5(sp)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/openssl/crypto/md5/asm/
H A Dmd5-sparcv9.S55 #define R5 %l5 define
71 #define Aval R5 /* those not used at the end of the last round */
189 LOAD X(5),R5
203 add T1,R5,T1 !=
401 !pre-LOADed X(5),R5
414 add T1,R5,T1
569 !pre-LOADed X(5),R5
583 add T1,R5,T1
820 !pre-LOADed X(5),R5
832 add T1,R5,T
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/timemachine/openssl-0.9.8e/crypto/md5/asm/
H A Dmd5-sparcv9.S55 #define R5 %l5 define
71 #define Aval R5 /* those not used at the end of the last round */
189 LOAD X(5),R5
203 add T1,R5,T1 !=
401 !pre-LOADed X(5),R5
414 add T1,R5,T1
569 !pre-LOADed X(5),R5
583 add T1,R5,T1
820 !pre-LOADed X(5),R5
832 add T1,R5,T
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/tc/
H A Dzs.c272 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
284 write_zsreg(channel, R5, regs[R5]);
672 info->zs_channel->curregs[R5] |= TxENAB;
676 write_zsreg(info->zs_channel, R5, info->zs_channel->curregs[R5]);
2018 info->zs_channel->curregs[R5] |= Tx7;
2021 info->zs_channel->curregs[R5] |= Tx8;
2040 info->zs_channel->curregs[R5] |
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ia64/kernel/
H A Dentry.h54 .spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off); \
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/wan/
H A Dz85230.h30 #define R5 5 macro
184 #define PRIME 1 /* R5' etc register access (Z85C30/230 only) */

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