Searched refs:R0 (Results 1 - 25 of 77) sorted by relevance

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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/lib/
H A Dumulsi3_highpart.S12 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU);
13 R0 = R1.L * R0.L, R1 = R1.H * R0.L (FU); define
14 R0 >>= 16;
17 R0 = R0 + R3; define
18 R0 = R0 define
22 R0 = R1 + R2; define
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H A Ddivsi3.S20 * Operand : R0 - Numerator (i)
22 * R0 - Quotient (o)
59 R3 = R0 ^ R1;
60 R0 = ABS R0; define
77 DIVS(R0, R1);
78 DIVQ(R0, R1);
79 DIVQ(R0, R1);
80 DIVQ(R0, R1);
81 DIVQ(R0, R
95 R0 = R0.L (Z); define
138 R0 = 0 ; /* Clear msw partial remainder */ define
145 R0 = R0 << 1 || R5 = [SP]; define
146 R0 = R0 | R7; /* and add carry */ define
150 R0 = R0 + R5; /* do add or subtract, as indicated by AQ */ define
181 R0 = R2; /* Return an identity value */ define
207 R0 = LSHIFT R0 by R1.L; define
216 R0 = 0; define
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H A Douts.S35 P0 = R0; /* P0 = port */
40 .Llong_loop_s: R0 = [P1++];
41 .Llong_loop_e: [P0] = R0;
46 P0 = R0; /* P0 = port */
51 .Lword_loop_s: R0 = W[P1++];
52 .Lword_loop_e: W[P0] = R0;
57 P0 = R0; /* P0 = port */
62 .Lbyte_loop_s: R0 = B[P1++];
63 .Lbyte_loop_e: B[P0] = R0;
H A Dumodsi3.S42 CC=R0==0;
46 CC=R0==R1;
50 CC = R0<R1 (IU);
51 IF CC JUMP .LRETURN_R0; /* Return dividend (R0),IF NR<DR */
55 R7 = R0; /* Copy of R0 */
60 R0 *= R6; /* Quotient * divisor */
61 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
66 R0 define
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H A Dudivsi3.S43 CC = R0 < R1 (IU); /* If X < Y, always return 0 */
47 CC = R2 <= R0 (IU);
50 R2 = R0 >> 31; /* if X is a 31-bit number */
69 R0 <<= 1;
70 DIVQ(R0, R1); // 1
71 DIVQ(R0, R1); // 2
72 DIVQ(R0, R1); // 3
73 DIVQ(R0, R1); // 4
74 DIVQ(R0, R1); // 5
75 DIVQ(R0, R
86 R0 = R0.L (Z); define
203 R0 = R2; /* Store quotient */ define
220 R0 = R2; define
243 R0 = LSHIFT R0 by R1.L; define
288 R0 = R3; /* Copy Q into result reg */ define
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H A Dmodsi3.S11 * Numerator/ Denominator in R0, R1
12 * R0 - returns remainder.
49 CC=R0==0;
53 CC=R0==R1;
65 R7 = R0; /* Copy of R0 */
70 R0 *= R6; /* Quotient * divisor */
71 R0 = R7 - R0; /* Dividend - (quotient * divisor) */ define
77 R0 define
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H A Dsmulsi3_highpart.S12 R2 = R1.L * R0.L (FU);
13 R3 = R1.H * R0.L (IS,M);
14 R0 = R0.H * R1.H, R1 = R0.H * R1.L (IS,M); define
29 R0 = R0 + R1; define
H A Dmemcmp.S33 * R0 = First Address (s1)
46 P0 = R0; /* P0 = s1 address */
52 R1 = R1 | R0; /* OR addresses together */
65 R0 = [P0++]; define
68 MNOP || R0 = [P0++] || R1 = [I0++];
70 CC = R0 == R1;
84 R0 = B[P0++](Z); /* *s1 */ define
85 CC = R0 == R1;
91 R0 = R0 define
111 R0 = 0; define
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H A Dmemchr.S33 * R0 = address (s)
45 P0 = R0; /* P0 = address */
62 R0=0;
66 R0 = P0; define
67 R0 += -1;
H A Dins.S37 P0 = R0; /* P0 = port */
43 .Llong_loop_s: R0 = [P0];
44 [P1++] = R0;
52 P0 = R0; /* P0 = port */
58 .Lword_loop_s: R0 = W[P0];
59 W[P1++] = R0;
67 P0 = R0; /* P0 = port */
73 .Lbyte_loop_s: R0 = B[P0];
74 B[P1++] = R0;
H A Dmemset.S42 * R0 = address (leave unchanged to form result)
49 P0 = R0 ; /* P0 = address */
51 R3 = R0 + R2; /* end */
56 R2 = R0 & R2; /* addr bottom two bits */
94 CC = BITTST (R0, 0); /* odd byte */
95 R0 = 4; define
96 R0 = R0 - R2; define
97 P1 = R0;
98 R0 define
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H A Dmemcpy.S39 * R0 = To Address (dest) (leave unchanged to form result)
58 P0 = R0 ; /* dst*/
63 CC = R1 < R0; /* src < dst */
66 CC = R0 < R3; /* and dst < src+len */
72 R3 = R1 | R0;
73 R0 = 0x3; define
74 R3 = R3 & R0;
86 R0 = R1; /* setup src address for return */ define
98 R0 = R1; define
123 R0 define
138 R0 = R1; /* save src for later. */ define
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-common/
H A Dcacheinit.S61 R0 = [I2++]; define
62 CC = R0 == R1;
64 [I0++] = R0;
78 R0 = (IMC | ENICPLB); define
79 R0 = R0 | R1; define
85 [P0] = R0;
112 R0 = [I2++]; define
113 cc = R0 == R1;
115 [I0++] = R0;
128 R0 = DMEM_CNTR; define
130 R0 = R0 | R1; define
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H A Dcplbhdlr.S55 R0 = 2; /* is a write to data space*/ define
61 R0 = 0; /* is_data_miss == False*/ define
68 R0 = 1; /* is_data_miss == True*/ define
89 CC = R0 == 0;
97 R0 = CPLB_UNKNOWN_ERR; define
101 CC = R0 == CPLB_NO_UNLOCKED;
103 R0 = CPLB_NO_UNLOCKED; define
107 CC = R0 == CPLB_NO_ADDR_MATCH;
109 R0 = CPLB_NO_ADDR_MATCH; define
113 CC = R0
115 R0 = CPLB_PROT_VIOL; define
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H A Dcplbmgr.S67 CC = R0 == 2;
70 CC = R0 == 0;
97 R0 = [P0++]; /* Info for this CPLB*/ define
98 CC = BITTST(R0,0); /* Is the CPLB valid?*/
102 R2 = EXTRACT(R0,R3.L) (Z); /* Get page size*/
144 R0 = [P0++]; define
148 CC = BITTST(R0, 0); /* an invalid entry is good */
150 CC = BITTST(R0,1); /* but a locked entry isn't */
178 R0 = [P0]; define
179 [P0 - 4] = R0;
180 R0 = [P0 - 0x100]; define
207 R0 = I0; define
269 R0 = CPLB_RELOADED; define
275 R0 = CPLB_NO_ADDR_MATCH; define
279 R0 = CPLB_NO_UNLOCKED; define
283 R0 = CPLB_PROT_VIOL; define
348 R0 = CPLB_RELOADED; define
395 R0 = [I2++]; /* Get the bits we're interested in*/ define
480 R0 = P0; define
493 R0 = [P0++]; /* move data */ define
495 R0 = [P0-0x104] /* move address */ define
504 R0 = I0; /* Our faulting address */ define
593 R0 = CPLB_RELOADED; define
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf537/boards/
H A Dled.S20 [--SP] = R0;
28 R0 = W[P0](Z); define
30 R0 = R0 & R2; define
31 W[P0] = R0.L;
36 R0 = W[P0](Z); define
38 R0 = R0 | R1; define
39 W[P0] = R0.L;
44 R0 define
46 R0 = R0 & R2; define
52 R0 = [SP++]; define
71 R0 = W[P0](Z); define
73 R0 = R0 | R1; define
95 R0 = W[P0](Z); define
97 R0 = R0 & R1; define
118 R0 = W[P0](Z); define
120 R0 = R0 ^ R1; define
138 R0 = R0 & R1; define
167 R0 = R0 & R1; define
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/
H A Dentry.h29 [--sp] = R0; /*orig_r0*/ \
31 R0 = (N); \
40 [--sp] = R0; /*orig_r0*/ \
45 R0 = (N); \
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
54 R0 = 0x36; define
55 SYSCFG = R0;
56 R0 = 0; define
59 R1 = R0;
60 R2 = R0;
61 R3 = R0;
62 R4 = R0;
63 R5 = R0;
100 R0 = ~ENICPLB; define
101 R0 = R0 & R1; define
118 R0 = ~ENDCPLB; define
119 R0 = R0 & R1; define
264 R0 = R7; define
328 R0 = [P2]; define
352 R0 = W[P0](Z); define
377 R0 = [P2]; define
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
54 R0 = 0x36; define
55 SYSCFG = R0;
56 R0 = 0; define
59 R1 = R0;
60 R2 = R0;
61 R3 = R0;
62 R4 = R0;
63 R5 = R0;
100 R0 = ~ENICPLB; define
101 R0 = R0 & R1; define
118 R0 = ~ENDCPLB; define
119 R0 = R0 & R1; define
142 R0 = (PGDE_UART | PFTE_UART)(Z); define
156 R0 = 0x000F(Z); define
179 R0 = 0x0000; define
318 R0 = R7; define
392 R0 = [P2]; define
416 R0 = W[P0](Z); define
441 R0 = [P2]; define
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/minidlna/ffmpeg-0.5.1/libavcodec/bfin/
H A Didct_bfin.S27 Registers Used : A0, A1, R0-R7, I0-I3, B0, B2, B3, M0-M2, L0-L3, P0-P5, LC0.
97 B0 = R0; // Pointer to Input matrix
110 I2 += M3 || R0.H = W[I0];
111 // Element 0 is read into R0.H
113 I1 += 4 || R0.L = W[I2++];
115 // Element 4 is read into R0.L.
139 A1=R7.H*R0.H, A0=R7.H*R0.H (IS) || I0+= 4 || R1.L=W[I1++];
140 R3=(A1+=R7.H*R0.L), R2=(A0-=R7.H*R0
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H A Dvp3_idct_bfin.S27 Registers Used : A0, A1, R0-R7, I0-I3, B0, B2, B3, M0-M2, L0-L3, P0-P5, LC0.
70 B0 = R0; // Pointer to Input matrix
83 I2 += M3 || R0.H = W[I0];
84 // Element 0 is read into R0.H
86 I1 += 4 || R0.L = W[I2++];
88 // Element 4 is read into R0.L.
112 A1=R7.H*R0.H, A0=R7.H*R0.H (IS) || I0+= 4 || R1.L=W[I1++];
113 R3=(A1+=R7.H*R0.L), R2=(A0-=R7.H*R0
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H A Dfdct_bfin.S60 R0, R1, R2, R3, R4, R5, R6,R7, P0, P1, P2, P3, P4, P5, A0, A1.
198 I1 = B0; // Element 1 and 0 is read in R0.
199 I1 += M0 || R0 = [I0++]; // I1 points to Input Element (0, 6).
223 R0 = R0 +|+ R3, R3 = R0 -|- R3 || R1.L = W[I0++] || NOP; define
236 * At the end of stage 1 R0 has (1,0), R1 has (2,3), R2 has (4, 5) and
247 R0 = R0 +|+ R1, R1 = R0 define
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S52 /* R0: argument of command line string, passed from uboot, save it */
53 R7 = R0;
57 R0 = 0x36; define
58 SYSCFG = R0;
59 R0 = 0; define
62 R1 = R0;
63 R2 = R0;
64 R3 = R0;
65 R4 = R0;
66 R5 = R0;
145 R0 = ~ENICPLB; define
146 R0 = R0 & R1; define
163 R0 = ~ENDCPLB; define
164 R0 = R0 & R1; define
309 R0 = R7; define
374 R0 = [P2]; define
398 R0 = W[P0](Z); define
423 R0 = [P2]; define
541 R0 = W[P0](Z); define
696 R0 = R2; define
699 R0 = R0 & R4; define
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/x86_64/crypto/
H A Dtwofish-x86_64-asm.S41 #define R0 %rax define
243 encrypt_round(R0,R1,R2,R3,0);
244 encrypt_round(R2,R3,R0,R1,8);
245 encrypt_round(R0,R1,R2,R3,2*8);
246 encrypt_round(R2,R3,R0,R1,3*8);
247 encrypt_round(R0,R1,R2,R3,4*8);
248 encrypt_round(R2,R3,R0,R1,5*8);
249 encrypt_round(R0,R1,R2,R3,6*8);
250 encrypt_round(R2,R3,R0,R1,7*8);
251 encrypt_round(R0,R
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/ap/gpl/openssl/crypto/md4/
H A Dmd4_dgst.c99 R0(A,B,C,D,X[ 0], 3,0);
100 R0(D,A,B,C,X[ 1], 7,0);
101 R0(C,D,A,B,X[ 2],11,0);
102 R0(B,C,D,A,X[ 3],19,0);
103 R0(A,B,C,D,X[ 4], 3,0);
104 R0(D,A,B,C,X[ 5], 7,0);
105 R0(C,D,A,B,X[ 6],11,0);
106 R0(B,C,D,A,X[ 7],19,0);
107 R0(A,B,C,D,X[ 8], 3,0);
108 R0(
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