Lines Matching refs:R0
49 /* R0: argument of command line string, passed from uboot, save it */
50 R7 = R0;
54 R0 = 0x36;
55 SYSCFG = R0;
56 R0 = 0;
59 R1 = R0;
60 R2 = R0;
61 R3 = R0;
62 R4 = R0;
63 R5 = R0;
64 R6 = R0;
66 P0 = R0;
67 P1 = R0;
68 P2 = R0;
69 P3 = R0;
70 P4 = R0;
71 P5 = R0;
100 R0 = ~ENICPLB;
101 R0 = R0 & R1;
108 [p0] = R0;
118 R0 = ~ENDCPLB;
119 R0 = R0 & R1;
126 [p0] = R0;
139 R0.L = W[P0]; /* Read */
142 R0 = (PGDE_UART | PFTE_UART)(Z);
144 W[P0] = R0.L; /* Write */
147 W[P0] = R0.L; /* Enable both UARTS */
153 R0.L = W[P0]; /* Read */
156 R0 = 0x000F(Z);
158 W[P0] = R0.L; /* Write */
162 W[P0] = R0.L;
168 R0.h = 0xFFFF; /* Clear EMAC Interrupt Status bits */
169 R0.l = 0xFFFF;
170 [P0] = R0;
177 R0.L = W[P0]; /* Read */
179 R0 = 0x0000;
180 W[P0] = R0.L; /* Write */
182 W[P0] = R0.L; /* Disable peripheral function of PORTH */
318 R0 = R7;
392 R0 = [P2];
393 BITSET (R0, 24);
394 [P2] = R0;
416 R0 = W[P0](Z);
417 CC = BITTST(R0,5);
441 R0 = [P2];
442 BITCLR (R0, 24);
449 BITSET (R0, 23);
451 [P2] = R0;
454 R0.L = lo(mem_SDGCTL);
455 R0.H = hi(mem_SDGCTL);
457 R1 = R1 | R0;
529 R0.l = 0x0;
530 W[P0] = R0.l;
541 R0.l = 0x0000;
542 W[P0] = R0;