Searched refs:PLL_CTL (Results 1 - 14 of 14) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-common/
H A Ddpmc.S177 P0.H = hi(PLL_CTL);
178 P0.L = lo(PLL_CTL);
193 P0.H = hi(PLL_CTL);
194 P0.L = lo(PLL_CTL);
245 P0.H = hi(PLL_CTL);
246 P0.L = lo(PLL_CTL);
263 P0.H = hi(PLL_CTL);
264 P0.L = lo(PLL_CTL);
300 P0.H = hi(PLL_CTL);
301 P0.L = lo(PLL_CTL);
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S308 * Set PLL_CTL
341 p0.h = hi(PLL_CTL);
342 p0.l = lo(PLL_CTL); /* Load the address */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S354 * Set PLL_CTL
387 p0.h = hi(PLL_CTL);
388 p0.l = lo(PLL_CTL); /* Load the address */
530 p0.h = hi(PLL_CTL);
531 p0.l = lo(PLL_CTL); /* Load the address */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S372 * Set PLL_CTL
405 p0.h = hi(PLL_CTL);
406 p0.l = lo(PLL_CTL); /* Load the address */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A DcdefBF532.h47 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
48 #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
H A DdefBF532.h58 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
404 /* PLL_CTL Masks */
418 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h38 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
39 #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
H A DdefBF52x_base.h42 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
613 /* PLL_CTL Masks */
622 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A DdefBF561.h48 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ macro
844 /* PLL_CTL Masks */
H A DcdefBF561.h52 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
53 #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h44 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
45 #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
H A DdefBF534.h41 #define PLL_CTL 0xFFC00000 /* PLL Control Register */ macro
985 /* PLL_CTL Masks */
994 /* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf548/
H A DcdefBF54x_base.h42 #define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
43 #define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
H A DdefBF54x_base.h41 #define PLL_CTL 0xffc00000 /* PLL Control Register */ macro
2549 /* Bit masks for PLL_CTL */

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