Searched refs:NCR5380_read (Results 1 - 21 of 21) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/scsi/
H A Dmac_scsi.c325 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
333 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
423 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
424 && !(NCR5380_read(STATUS_REG) & SR_REQ))
426 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
427 && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {
515 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)
516 && (!(NCR5380_read(STATUS_REG) & SR_REQ)
517 || (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)))
519 if (!(NCR5380_read(BUS_AND_STATUS_RE
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H A Dmac_scsi.h68 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro
H A DNCR5380.c181 * NCR5380_read(register) - read from the specified register
268 r = NCR5380_read(reg);
277 r = NCR5380_read(reg);
356 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
357 status = NCR5380_read(STATUS_REG);
358 mr = NCR5380_read(MODE_REG);
359 icr = NCR5380_read(INITIATOR_COMMAND_REG);
360 basr = NCR5380_read(BUS_AND_STATUS_REG);
398 status = NCR5380_read(STATUS_REG);
835 for (pass = 1; (NCR5380_read(STATUS_RE
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H A Ddtc.h73 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
76 #define NCR5380_read(reg) (readb(DTC_address(reg))) macro
H A Dsun3_NCR5380.c117 * NCR5380_read(register) - read from the specified register
472 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
473 status = NCR5380_read(STATUS_REG);
474 mr = NCR5380_read(MODE_REG);
475 icr = NCR5380_read(INITIATOR_COMMAND_REG);
476 basr = NCR5380_read(BUS_AND_STATUS_REG);
518 status = NCR5380_read(STATUS_REG);
1093 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG),
1094 NCR5380_read(STATUS_REG));
1104 if((NCR5380_read(BUS_AND_STATUS_RE
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H A Datari_NCR5380.c123 * NCR5380_read(register) - read from the specified register
474 data = NCR5380_read(CURRENT_SCSI_DATA_REG);
475 status = NCR5380_read(STATUS_REG);
476 mr = NCR5380_read(MODE_REG);
477 icr = NCR5380_read(INITIATOR_COMMAND_REG);
478 basr = NCR5380_read(BUS_AND_STATUS_REG);
521 status = NCR5380_read(STATUS_REG);
1117 if ((NCR5380_read(BUS_AND_STATUS_REG) &
1120 saved_data = NCR5380_read(INPUT_DATA_REG);
1128 HOSTNO, NCR5380_read(BUS_AND_STATUS_RE
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H A Dg_NCR5380.c570 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) {
573 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) {
577 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY);
583 dst[start + i] = NCR5380_read(C400_HOST_BUFFER);
594 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)
602 dst[start + i] = NCR5380_read(C400_HOST_BUFFER);
612 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ))
615 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER))
619 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
646 if (NCR5380_read(C400_CONTROL_STATUS_RE
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H A Dt128.h128 #define NCR5380_read(reg) readb(T128_address(reg)) macro
131 #define NCR5380_read(reg) \ macro
H A Ddtc.c361 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
371 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
382 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))
386 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
411 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
422 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY)
430 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS))
434 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT))
H A Dg_NCR5380.h84 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro
109 #define NCR5380_read(reg) readb(iomem + NCR53C400_mem_base + (reg)) macro
H A Dpas16.h146 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro
149 #define NCR5380_read(reg) \ macro
H A Dsun3_scsi.c344 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
354 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
559 if(count && (NCR5380_read(BUS_AND_STATUS_REG) &
562 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG));
H A Dpas16.c250 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
327 if( NCR5380_read( MODE_REG ) != 0x20 ) /* Write to a reg. */
330 if( NCR5380_read( MODE_REG ) != 0x00 )
H A Ddmx3191d.c38 #define NCR5380_read(reg) inb(port + reg) macro
H A Datari_scsi.h49 #define NCR5380_read(reg) atari_scsi_reg_read( reg ) macro
H A Dsun3_scsi_vme.c310 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
320 NCR5380_read( RESET_PARITY_INTERRUPT_REG );
H A Dsun3_scsi.h100 #define NCR5380_read(reg) sun3scsi_read(reg) macro
H A Datari_scsi.c823 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG)));
831 NCR5380_read(RESET_PARITY_INTERRUPT_REG);
1054 * methods are quite different. The calling macros NCR5380_read and
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/scsi/arm/
H A Decoscsi.c41 #define NCR5380_read(reg) ecoscsi_read(_instance, reg) macro
H A Doak.c26 #define NCR5380_read(reg) oakscsi_read(_instance, reg) macro
H A Dcumana_1.c30 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro

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