Searched refs:MII_BMCR (Results 1 - 25 of 56) sorted by relevance

123

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/chelsio/
H A Dmv88e1xxx.c52 mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
55 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
128 (void) simple_mdio_read(phy, MII_BMCR, &ctl);
143 (void) simple_mdio_write(phy, MII_BMCR, ctl);
166 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
169 (void) simple_mdio_write(cphy, MII_BMCR, ctl);
187 (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
189 (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
195 mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
234 mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBAC
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/cxgb3/
H A Dvsc8211.c105 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
111 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
121 err = mdio_read(cphy, 0, MII_BMCR, &bmcr);
189 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
H A Dael1002.c62 err = t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
163 return t3_mdio_change_bits(phy, MDIO_DEV_PMA_PMD, MII_BMCR,
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/ibm_emac/
H A Dibm_emac_phy.c39 * polls MII_BMCR until BMCR_RESET bit clears or operation times out.
52 val = phy_read(phy, MII_BMCR);
71 val = phy_read(phy, MII_BMCR);
74 phy_write(phy, MII_BMCR, val);
80 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE);
130 * causes BMCR_RESET to be set on the next read of MII_BMCR, which
137 phy_write(phy, MII_BMCR, ctl);
154 ctl = phy_read(phy, MII_BMCR);
174 phy_write(phy, MII_BMCR, ctl);
232 int bmcr = phy_read(phy, MII_BMCR);
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/
H A Dsungem_phy.c75 val = __phy_read(phy, phy_id, MII_BMCR);
78 __phy_write(phy, phy_id, MII_BMCR, val);
83 val = __phy_read(phy, phy_id, MII_BMCR);
89 __phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
292 phy_write(phy, MII_BMCR, BMCR_RESET);
293 phy_write(phy, MII_BMCR, 0x1340);
331 ctl = phy_read(phy, MII_BMCR);
333 phy_write(phy, MII_BMCR, ctl);
347 ctl = phy_read(phy, MII_BMCR);
351 phy_write(phy, MII_BMCR, ct
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H A Dmii.c84 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
195 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
197 mii->mdio_write(dev, mii->phy_id, MII_BMCR, bmcr);
204 bmcr = mii->mdio_read(dev, mii->phy_id, MII_BMCR);
217 mii->mdio_write(dev, mii->phy_id, MII_BMCR, tmp);
269 bmcr = mii->mdio_read(mii->dev, mii->phy_id, MII_BMCR);
273 mii->mdio_write(mii->dev, mii->phy_id, MII_BMCR, bmcr);
418 case MII_BMCR: {
H A Dtc35815.c1123 tc_mdio_write(dev, pid, MII_BMCR, BMCR_RESET);
1126 if (!(tc_mdio_read(dev, pid, MII_BMCR) & BMCR_RESET))
2234 bmcr = tc_mdio_read(dev, pid, MII_BMCR);
2240 tc_mdio_write(dev, pid, MII_BMCR, bmcr);
2248 tc_mdio_write(dev, pid, MII_BMCR, bmcr);
2265 bmcr = tc_mdio_read(dev, pid, MII_BMCR);
2290 bmcr = tc_mdio_read(dev, pid, MII_BMCR);
2316 bmcr = tc_mdio_read(dev, pid, MII_BMCR);
2337 bmcr = tc_mdio_read(dev, pid, MII_BMCR);
2400 tc_mdio_read(dev, pid, MII_BMCR),
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H A Ddl2k.c1485 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1543 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1548 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1558 bmcr.image = mii_read (dev, phy_addr, MII_BMCR);
1560 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1564 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1589 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1677 mii_write (dev, phy_addr, MII_BMCR, MII_BMCR_RESET);
1682 mii_write (dev, phy_addr, MII_BMCR, bmcr.image);
1689 mii_write (dev, phy_addr, MII_BMCR, bmc
[all...]
H A Dsunhme.c547 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
554 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
561 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
599 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
631 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
704 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
708 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
998 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1000 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1014 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
[all...]
H A Dcassini.c467 u16 ctl = cas_phy_read(cp, MII_BMCR);
472 cas_phy_write(cp, MII_BMCR, ctl);
477 u16 ctl = cas_phy_read(cp, MII_BMCR);
482 cas_phy_write(cp, MII_BMCR, ctl);
769 ctl = cas_phy_read(cp, MII_BMCR);
780 cas_phy_write(cp, MII_BMCR, ctl);
794 cas_phy_write(cp, MII_BMCR, BMCR_RESET);
797 val = cas_phy_read(cp, MII_BMCR);
853 cas_phy_write(cp, MII_BMCR, 0x00f1);
894 val = cas_phy_read(cp, MII_BMCR);
[all...]
H A Dsis190.c915 val = mdio_read(ioaddr, phy_id, MII_BMCR);
923 mdio_write(ioaddr, phy_id, MII_BMCR, val | BMCR_RESET);
1256 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1257 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1283 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1286 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1686 mdio_write(ioaddr, phy_id, MII_BMCR,
H A Deepro100.c756 mdio_write(dev, eeprom[6] & 0x1f, MII_BMCR,
996 mdio_write(dev, phy_addr, MII_BMCR, mii_ctrl[dev->default_port & 7]);
998 mdio_write(dev, phy_addr, MII_BMCR, 0x3300);
1040 mdio_read(dev, sp->phy[0] & 0x1f, MII_BMCR);
1322 int mii_bmcr = mdio_read(dev, phy_addr, MII_BMCR);
1323 mdio_write(dev, phy_addr, MII_BMCR, 0x0400);
1326 mdio_write(dev, phy_addr, MII_BMCR, 0x8000);
1328 mdio_write(dev, phy_addr, MII_BMCR, mii_ctrl[dev->default_port & 7]);
1330 mdio_read(dev, phy_addr, MII_BMCR);
1331 mdio_write(dev, phy_addr, MII_BMCR, mii_bmc
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H A Dtsi108_eth.c1251 tsi108_write_mii(data, MII_BMCR, BMCR_RESET);
1253 if(!(tsi108_read_mii(data, MII_BMCR) & BMCR_RESET))
1267 MII_BMCR,
1269 while (tsi108_read_mii(data, MII_BMCR) & BMCR_ANRESTART)
1305 tsi108_write_mii(data, MII_BMCR, BMCR_PDOWN);
H A Dsmc91x.c1007 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
1036 smc_phy_write(dev, phy, MII_BMCR, BMCR_RESET);
1043 bmcr = smc_phy_read(dev, phy, MII_BMCR);
1078 bmcr = smc_phy_read(dev, phy, MII_BMCR);
1079 smc_phy_write(dev, phy, MII_BMCR, bmcr | BMCR_PDOWN);
1206 smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
H A Dstarfire.c875 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
879 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
1110 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1112 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1119 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1134 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1603 mdio_read(dev, np->phys[0], MII_BMCR);
1606 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/phy/
H A Ddavicom.c90 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
109 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE);
127 err = phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
H A Dphy_device.c361 * Description: Configures MII_BMCR to force speed/duplex
379 ctl = phy_write(phydev, MII_BMCR, ctl);
401 ctl = phy_read(phydev, MII_BMCR);
411 ctl = phy_write(phydev, MII_BMCR, ctl);
549 int bmcr = phy_read(phydev, MII_BMCR);
H A Dmarvell.c100 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
172 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
H A Dfixed.c133 regs[MII_BMCR] = bmcr;
H A Dphy.c376 case MII_BMCR:
403 if (mii_data->reg_num == MII_BMCR
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/8260_io/
H A Dfcc_enet.c880 { mk_mii_write(MII_BMCR, BMCR_ANENABLE), mii_parse_cr },
885 { mk_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART),
943 { mk_mii_read(MII_BMCR), mii_parse_cr },
949 { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */
1025 { mk_mii_write(MII_BMCR, BMCR_ANENABLE), mii_parse_cr },
1032 { mk_mii_write(MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART),
1100 { mk_mii_read(MII_BMCR), mii_parse_cr },
1106 { mk_mii_write(MII_BMCR, 0x1200), NULL }, /* autonegotiate */
1169 { mk_mii_read(MII_BMCR), mii_parse_cr },
1175 { mk_mii_write(MII_BMCR,
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/tulip/
H A Dmedia.c280 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
307 (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
481 mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
552 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
555 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
H A Dxircom_tulip_cb.c457 int mii_reg0 = mdio_read(dev, phy, MII_BMCR);
963 mdio_read(dev, tp->phys[0], MII_BMCR);
966 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
1021 mdio_write(dev, tp->phys[0], MII_BMCR, BMCR_RESET);
1023 while (mdio_read(dev, tp->phys[0], MII_BMCR) & BMCR_RESET);
1025 reg0 = mdio_read(dev, tp->phys[0], MII_BMCR);
1042 mdio_write(dev, tp->phys[0], MII_BMCR, reg0);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/usb/
H A Dmcs7830.c271 ret = mcs7830_write_phy(dev, MII_BMCR, 0x0000);
274 ret = mcs7830_write_phy(dev, MII_BMCR, BMCR_ANENABLE);
277 ret = mcs7830_write_phy(dev, MII_BMCR,
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/linux/
H A Dmii.h15 #define MII_BMCR 0x00 /* Basic mode control register */ macro

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