1/* cassini.c: Sun Microsystems Cassini(+) ethernet driver. 2 * 3 * Copyright (C) 2004 Sun Microsystems Inc. 4 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com) 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of the 9 * License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 19 * 02111-1307, USA. 20 * 21 * This driver uses the sungem driver (c) David Miller 22 * (davem@redhat.com) as its basis. 23 * 24 * The cassini chip has a number of features that distinguish it from 25 * the gem chip: 26 * 4 transmit descriptor rings that are used for either QoS (VLAN) or 27 * load balancing (non-VLAN mode) 28 * batching of multiple packets 29 * multiple CPU dispatching 30 * page-based RX descriptor engine with separate completion rings 31 * Gigabit support (GMII and PCS interface) 32 * MIF link up/down detection works 33 * 34 * RX is handled by page sized buffers that are attached as fragments to 35 * the skb. here's what's done: 36 * -- driver allocates pages at a time and keeps reference counts 37 * on them. 38 * -- the upper protocol layers assume that the header is in the skb 39 * itself. as a result, cassini will copy a small amount (64 bytes) 40 * to make them happy. 41 * -- driver appends the rest of the data pages as frags to skbuffs 42 * and increments the reference count 43 * -- on page reclamation, the driver swaps the page with a spare page. 44 * if that page is still in use, it frees its reference to that page, 45 * and allocates a new page for use. otherwise, it just recycles the 46 * the page. 47 * 48 * NOTE: cassini can parse the header. however, it's not worth it 49 * as long as the network stack requires a header copy. 50 * 51 * TX has 4 queues. currently these queues are used in a round-robin 52 * fashion for load balancing. They can also be used for QoS. for that 53 * to work, however, QoS information needs to be exposed down to the driver 54 * level so that subqueues get targetted to particular transmit rings. 55 * alternatively, the queues can be configured via use of the all-purpose 56 * ioctl. 57 * 58 * RX DATA: the rx completion ring has all the info, but the rx desc 59 * ring has all of the data. RX can conceivably come in under multiple 60 * interrupts, but the INT# assignment needs to be set up properly by 61 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do 62 * that. also, the two descriptor rings are designed to distinguish between 63 * encrypted and non-encrypted packets, but we use them for buffering 64 * instead. 65 * 66 * by default, the selective clear mask is set up to process rx packets. 67 */ 68 69 70#include <linux/module.h> 71#include <linux/kernel.h> 72#include <linux/types.h> 73#include <linux/compiler.h> 74#include <linux/slab.h> 75#include <linux/delay.h> 76#include <linux/init.h> 77#include <linux/ioport.h> 78#include <linux/pci.h> 79#include <linux/mm.h> 80#include <linux/highmem.h> 81#include <linux/list.h> 82#include <linux/dma-mapping.h> 83 84#include <linux/netdevice.h> 85#include <linux/etherdevice.h> 86#include <linux/skbuff.h> 87#include <linux/ethtool.h> 88#include <linux/crc32.h> 89#include <linux/random.h> 90#include <linux/mii.h> 91#include <linux/ip.h> 92#include <linux/tcp.h> 93#include <linux/mutex.h> 94 95#include <net/checksum.h> 96 97#include <asm/atomic.h> 98#include <asm/system.h> 99#include <asm/io.h> 100#include <asm/byteorder.h> 101#include <asm/uaccess.h> 102 103#define cas_page_map(x) kmap_atomic((x), KM_SKB_DATA_SOFTIRQ) 104#define cas_page_unmap(x) kunmap_atomic((x), KM_SKB_DATA_SOFTIRQ) 105#define CAS_NCPUS num_online_cpus() 106 107#if defined(CONFIG_CASSINI_NAPI) && defined(HAVE_NETDEV_POLL) 108#define USE_NAPI 109#define cas_skb_release(x) netif_receive_skb(x) 110#else 111#define cas_skb_release(x) netif_rx(x) 112#endif 113 114/* select which firmware to use */ 115#define USE_HP_WORKAROUND 116#define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */ 117#define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */ 118 119#include "cassini.h" 120 121#define USE_TX_COMPWB /* use completion writeback registers */ 122#define USE_CSMA_CD_PROTO /* standard CSMA/CD */ 123#define USE_RX_BLANK /* hw interrupt mitigation */ 124#undef USE_ENTROPY_DEV /* don't test for entropy device */ 125 126/* NOTE: these aren't useable unless PCI interrupts can be assigned. 127 * also, we need to make cp->lock finer-grained. 128 */ 129#undef USE_PCI_INTB 130#undef USE_PCI_INTC 131#undef USE_PCI_INTD 132#undef USE_QOS 133 134#undef USE_VPD_DEBUG /* debug vpd information if defined */ 135 136/* rx processing options */ 137#define USE_PAGE_ORDER /* specify to allocate large rx pages */ 138#define RX_DONT_BATCH 0 /* if 1, don't batch flows */ 139#define RX_COPY_ALWAYS 0 /* if 0, use frags */ 140#define RX_COPY_MIN 64 /* copy a little to make upper layers happy */ 141#undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */ 142 143#define DRV_MODULE_NAME "cassini" 144#define PFX DRV_MODULE_NAME ": " 145#define DRV_MODULE_VERSION "1.4" 146#define DRV_MODULE_RELDATE "1 July 2004" 147 148#define CAS_DEF_MSG_ENABLE \ 149 (NETIF_MSG_DRV | \ 150 NETIF_MSG_PROBE | \ 151 NETIF_MSG_LINK | \ 152 NETIF_MSG_TIMER | \ 153 NETIF_MSG_IFDOWN | \ 154 NETIF_MSG_IFUP | \ 155 NETIF_MSG_RX_ERR | \ 156 NETIF_MSG_TX_ERR) 157 158/* length of time before we decide the hardware is borked, 159 * and dev->tx_timeout() should be called to fix the problem 160 */ 161#define CAS_TX_TIMEOUT (HZ) 162#define CAS_LINK_TIMEOUT (22*HZ/10) 163#define CAS_LINK_FAST_TIMEOUT (1) 164 165/* timeout values for state changing. these specify the number 166 * of 10us delays to be used before giving up. 167 */ 168#define STOP_TRIES_PHY 1000 169#define STOP_TRIES 5000 170 171/* specify a minimum frame size to deal with some fifo issues 172 * max mtu == 2 * page size - ethernet header - 64 - swivel = 173 * 2 * page_size - 0x50 174 */ 175#define CAS_MIN_FRAME 97 176#define CAS_1000MB_MIN_FRAME 255 177#define CAS_MIN_MTU 60 178#define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000) 179 180/* 181 * Eliminate these and use separate atomic counters for each, to 182 * avoid a race condition. 183 */ 184 185static char version[] __devinitdata = 186 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 187 188static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */ 189static int link_mode; 190 191MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)"); 192MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver"); 193MODULE_LICENSE("GPL"); 194module_param(cassini_debug, int, 0); 195MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value"); 196module_param(link_mode, int, 0); 197MODULE_PARM_DESC(link_mode, "default link mode"); 198 199#define DEFAULT_LINKDOWN_TIMEOUT 5 200/* 201 * Value in seconds, for user input. 202 */ 203static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT; 204module_param(linkdown_timeout, int, 0); 205MODULE_PARM_DESC(linkdown_timeout, 206"min reset interval in sec. for PCS linkdown issue; disabled if not positive"); 207 208/* 209 * value in 'ticks' (units used by jiffies). Set when we init the 210 * module because 'HZ' in actually a function call on some flavors of 211 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ. 212 */ 213static int link_transition_timeout; 214 215 216 217static u16 link_modes[] __devinitdata = { 218 BMCR_ANENABLE, /* 0 : autoneg */ 219 0, /* 1 : 10bt half duplex */ 220 BMCR_SPEED100, /* 2 : 100bt half duplex */ 221 BMCR_FULLDPLX, /* 3 : 10bt full duplex */ 222 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */ 223 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */ 224}; 225 226static struct pci_device_id cas_pci_tbl[] __devinitdata = { 227 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI, 228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 229 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN, 230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 231 { 0, } 232}; 233 234MODULE_DEVICE_TABLE(pci, cas_pci_tbl); 235 236static void cas_set_link_modes(struct cas *cp); 237 238static inline void cas_lock_tx(struct cas *cp) 239{ 240 int i; 241 242 for (i = 0; i < N_TX_RINGS; i++) 243 spin_lock(&cp->tx_lock[i]); 244} 245 246static inline void cas_lock_all(struct cas *cp) 247{ 248 spin_lock_irq(&cp->lock); 249 cas_lock_tx(cp); 250} 251 252/* WTZ: QA was finding deadlock problems with the previous 253 * versions after long test runs with multiple cards per machine. 254 * See if replacing cas_lock_all with safer versions helps. The 255 * symptoms QA is reporting match those we'd expect if interrupts 256 * aren't being properly restored, and we fixed a previous deadlock 257 * with similar symptoms by using save/restore versions in other 258 * places. 259 */ 260#define cas_lock_all_save(cp, flags) \ 261do { \ 262 struct cas *xxxcp = (cp); \ 263 spin_lock_irqsave(&xxxcp->lock, flags); \ 264 cas_lock_tx(xxxcp); \ 265} while (0) 266 267static inline void cas_unlock_tx(struct cas *cp) 268{ 269 int i; 270 271 for (i = N_TX_RINGS; i > 0; i--) 272 spin_unlock(&cp->tx_lock[i - 1]); 273} 274 275static inline void cas_unlock_all(struct cas *cp) 276{ 277 cas_unlock_tx(cp); 278 spin_unlock_irq(&cp->lock); 279} 280 281#define cas_unlock_all_restore(cp, flags) \ 282do { \ 283 struct cas *xxxcp = (cp); \ 284 cas_unlock_tx(xxxcp); \ 285 spin_unlock_irqrestore(&xxxcp->lock, flags); \ 286} while (0) 287 288static void cas_disable_irq(struct cas *cp, const int ring) 289{ 290 /* Make sure we won't get any more interrupts */ 291 if (ring == 0) { 292 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); 293 return; 294 } 295 296 /* disable completion interrupts and selectively mask */ 297 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 298 switch (ring) { 299#if defined(USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 300#ifdef USE_PCI_INTB 301 case 1: 302#endif 303#ifdef USE_PCI_INTC 304 case 2: 305#endif 306#ifdef USE_PCI_INTD 307 case 3: 308#endif 309 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, 310 cp->regs + REG_PLUS_INTRN_MASK(ring)); 311 break; 312#endif 313 default: 314 writel(INTRN_MASK_CLEAR_ALL, cp->regs + 315 REG_PLUS_INTRN_MASK(ring)); 316 break; 317 } 318 } 319} 320 321static inline void cas_mask_intr(struct cas *cp) 322{ 323 int i; 324 325 for (i = 0; i < N_RX_COMP_RINGS; i++) 326 cas_disable_irq(cp, i); 327} 328 329static inline void cas_buffer_init(cas_page_t *cp) 330{ 331 struct page *page = cp->buffer; 332 atomic_set((atomic_t *)&page->lru.next, 1); 333} 334 335static inline int cas_buffer_count(cas_page_t *cp) 336{ 337 struct page *page = cp->buffer; 338 return atomic_read((atomic_t *)&page->lru.next); 339} 340 341static inline void cas_buffer_inc(cas_page_t *cp) 342{ 343 struct page *page = cp->buffer; 344 atomic_inc((atomic_t *)&page->lru.next); 345} 346 347static inline void cas_buffer_dec(cas_page_t *cp) 348{ 349 struct page *page = cp->buffer; 350 atomic_dec((atomic_t *)&page->lru.next); 351} 352 353static void cas_enable_irq(struct cas *cp, const int ring) 354{ 355 if (ring == 0) { /* all but TX_DONE */ 356 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); 357 return; 358 } 359 360 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 361 switch (ring) { 362#if defined(USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 363#ifdef USE_PCI_INTB 364 case 1: 365#endif 366#ifdef USE_PCI_INTC 367 case 2: 368#endif 369#ifdef USE_PCI_INTD 370 case 3: 371#endif 372 writel(INTRN_MASK_RX_EN, cp->regs + 373 REG_PLUS_INTRN_MASK(ring)); 374 break; 375#endif 376 default: 377 break; 378 } 379 } 380} 381 382static inline void cas_unmask_intr(struct cas *cp) 383{ 384 int i; 385 386 for (i = 0; i < N_RX_COMP_RINGS; i++) 387 cas_enable_irq(cp, i); 388} 389 390static inline void cas_entropy_gather(struct cas *cp) 391{ 392#ifdef USE_ENTROPY_DEV 393 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) 394 return; 395 396 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV), 397 readl(cp->regs + REG_ENTROPY_IV), 398 sizeof(uint64_t)*8); 399#endif 400} 401 402static inline void cas_entropy_reset(struct cas *cp) 403{ 404#ifdef USE_ENTROPY_DEV 405 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) 406 return; 407 408 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, 409 cp->regs + REG_BIM_LOCAL_DEV_EN); 410 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET); 411 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG); 412 413 /* if we read back 0x0, we don't have an entropy device */ 414 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0) 415 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV; 416#endif 417} 418 419/* access to the phy. the following assumes that we've initialized the MIF to 420 * be in frame rather than bit-bang mode 421 */ 422static u16 cas_phy_read(struct cas *cp, int reg) 423{ 424 u32 cmd; 425 int limit = STOP_TRIES_PHY; 426 427 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ; 428 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); 429 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); 430 cmd |= MIF_FRAME_TURN_AROUND_MSB; 431 writel(cmd, cp->regs + REG_MIF_FRAME); 432 433 /* poll for completion */ 434 while (limit-- > 0) { 435 udelay(10); 436 cmd = readl(cp->regs + REG_MIF_FRAME); 437 if (cmd & MIF_FRAME_TURN_AROUND_LSB) 438 return (cmd & MIF_FRAME_DATA_MASK); 439 } 440 return 0xFFFF; /* -1 */ 441} 442 443static int cas_phy_write(struct cas *cp, int reg, u16 val) 444{ 445 int limit = STOP_TRIES_PHY; 446 u32 cmd; 447 448 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE; 449 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); 450 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); 451 cmd |= MIF_FRAME_TURN_AROUND_MSB; 452 cmd |= val & MIF_FRAME_DATA_MASK; 453 writel(cmd, cp->regs + REG_MIF_FRAME); 454 455 /* poll for completion */ 456 while (limit-- > 0) { 457 udelay(10); 458 cmd = readl(cp->regs + REG_MIF_FRAME); 459 if (cmd & MIF_FRAME_TURN_AROUND_LSB) 460 return 0; 461 } 462 return -1; 463} 464 465static void cas_phy_powerup(struct cas *cp) 466{ 467 u16 ctl = cas_phy_read(cp, MII_BMCR); 468 469 if ((ctl & BMCR_PDOWN) == 0) 470 return; 471 ctl &= ~BMCR_PDOWN; 472 cas_phy_write(cp, MII_BMCR, ctl); 473} 474 475static void cas_phy_powerdown(struct cas *cp) 476{ 477 u16 ctl = cas_phy_read(cp, MII_BMCR); 478 479 if (ctl & BMCR_PDOWN) 480 return; 481 ctl |= BMCR_PDOWN; 482 cas_phy_write(cp, MII_BMCR, ctl); 483} 484 485/* cp->lock held. note: the last put_page will free the buffer */ 486static int cas_page_free(struct cas *cp, cas_page_t *page) 487{ 488 pci_unmap_page(cp->pdev, page->dma_addr, cp->page_size, 489 PCI_DMA_FROMDEVICE); 490 cas_buffer_dec(page); 491 __free_pages(page->buffer, cp->page_order); 492 kfree(page); 493 return 0; 494} 495 496#ifdef RX_COUNT_BUFFERS 497#define RX_USED_ADD(x, y) ((x)->used += (y)) 498#define RX_USED_SET(x, y) ((x)->used = (y)) 499#else 500#define RX_USED_ADD(x, y) 501#define RX_USED_SET(x, y) 502#endif 503 504/* local page allocation routines for the receive buffers. jumbo pages 505 * require at least 8K contiguous and 8K aligned buffers. 506 */ 507static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags) 508{ 509 cas_page_t *page; 510 511 page = kmalloc(sizeof(cas_page_t), flags); 512 if (!page) 513 return NULL; 514 515 INIT_LIST_HEAD(&page->list); 516 RX_USED_SET(page, 0); 517 page->buffer = alloc_pages(flags, cp->page_order); 518 if (!page->buffer) 519 goto page_err; 520 cas_buffer_init(page); 521 page->dma_addr = pci_map_page(cp->pdev, page->buffer, 0, 522 cp->page_size, PCI_DMA_FROMDEVICE); 523 return page; 524 525page_err: 526 kfree(page); 527 return NULL; 528} 529 530/* initialize spare pool of rx buffers, but allocate during the open */ 531static void cas_spare_init(struct cas *cp) 532{ 533 spin_lock(&cp->rx_inuse_lock); 534 INIT_LIST_HEAD(&cp->rx_inuse_list); 535 spin_unlock(&cp->rx_inuse_lock); 536 537 spin_lock(&cp->rx_spare_lock); 538 INIT_LIST_HEAD(&cp->rx_spare_list); 539 cp->rx_spares_needed = RX_SPARE_COUNT; 540 spin_unlock(&cp->rx_spare_lock); 541} 542 543/* used on close. free all the spare buffers. */ 544static void cas_spare_free(struct cas *cp) 545{ 546 struct list_head list, *elem, *tmp; 547 548 /* free spare buffers */ 549 INIT_LIST_HEAD(&list); 550 spin_lock(&cp->rx_spare_lock); 551 list_splice(&cp->rx_spare_list, &list); 552 INIT_LIST_HEAD(&cp->rx_spare_list); 553 spin_unlock(&cp->rx_spare_lock); 554 list_for_each_safe(elem, tmp, &list) { 555 cas_page_free(cp, list_entry(elem, cas_page_t, list)); 556 } 557 558 INIT_LIST_HEAD(&list); 559 /* 560 * Looks like Adrian had protected this with a different 561 * lock than used everywhere else to manipulate this list. 562 */ 563 spin_lock(&cp->rx_inuse_lock); 564 list_splice(&cp->rx_inuse_list, &list); 565 INIT_LIST_HEAD(&cp->rx_inuse_list); 566 spin_unlock(&cp->rx_inuse_lock); 567 list_for_each_safe(elem, tmp, &list) { 568 cas_page_free(cp, list_entry(elem, cas_page_t, list)); 569 } 570} 571 572/* replenish spares if needed */ 573static void cas_spare_recover(struct cas *cp, const gfp_t flags) 574{ 575 struct list_head list, *elem, *tmp; 576 int needed, i; 577 578 /* check inuse list. if we don't need any more free buffers, 579 * just free it 580 */ 581 582 /* make a local copy of the list */ 583 INIT_LIST_HEAD(&list); 584 spin_lock(&cp->rx_inuse_lock); 585 list_splice(&cp->rx_inuse_list, &list); 586 INIT_LIST_HEAD(&cp->rx_inuse_list); 587 spin_unlock(&cp->rx_inuse_lock); 588 589 list_for_each_safe(elem, tmp, &list) { 590 cas_page_t *page = list_entry(elem, cas_page_t, list); 591 592 if (cas_buffer_count(page) > 1) 593 continue; 594 595 list_del(elem); 596 spin_lock(&cp->rx_spare_lock); 597 if (cp->rx_spares_needed > 0) { 598 list_add(elem, &cp->rx_spare_list); 599 cp->rx_spares_needed--; 600 spin_unlock(&cp->rx_spare_lock); 601 } else { 602 spin_unlock(&cp->rx_spare_lock); 603 cas_page_free(cp, page); 604 } 605 } 606 607 /* put any inuse buffers back on the list */ 608 if (!list_empty(&list)) { 609 spin_lock(&cp->rx_inuse_lock); 610 list_splice(&list, &cp->rx_inuse_list); 611 spin_unlock(&cp->rx_inuse_lock); 612 } 613 614 spin_lock(&cp->rx_spare_lock); 615 needed = cp->rx_spares_needed; 616 spin_unlock(&cp->rx_spare_lock); 617 if (!needed) 618 return; 619 620 /* we still need spares, so try to allocate some */ 621 INIT_LIST_HEAD(&list); 622 i = 0; 623 while (i < needed) { 624 cas_page_t *spare = cas_page_alloc(cp, flags); 625 if (!spare) 626 break; 627 list_add(&spare->list, &list); 628 i++; 629 } 630 631 spin_lock(&cp->rx_spare_lock); 632 list_splice(&list, &cp->rx_spare_list); 633 cp->rx_spares_needed -= i; 634 spin_unlock(&cp->rx_spare_lock); 635} 636 637/* pull a page from the list. */ 638static cas_page_t *cas_page_dequeue(struct cas *cp) 639{ 640 struct list_head *entry; 641 int recover; 642 643 spin_lock(&cp->rx_spare_lock); 644 if (list_empty(&cp->rx_spare_list)) { 645 /* try to do a quick recovery */ 646 spin_unlock(&cp->rx_spare_lock); 647 cas_spare_recover(cp, GFP_ATOMIC); 648 spin_lock(&cp->rx_spare_lock); 649 if (list_empty(&cp->rx_spare_list)) { 650 if (netif_msg_rx_err(cp)) 651 printk(KERN_ERR "%s: no spare buffers " 652 "available.\n", cp->dev->name); 653 spin_unlock(&cp->rx_spare_lock); 654 return NULL; 655 } 656 } 657 658 entry = cp->rx_spare_list.next; 659 list_del(entry); 660 recover = ++cp->rx_spares_needed; 661 spin_unlock(&cp->rx_spare_lock); 662 663 /* trigger the timer to do the recovery */ 664 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) { 665 atomic_inc(&cp->reset_task_pending); 666 atomic_inc(&cp->reset_task_pending_spare); 667 schedule_work(&cp->reset_task); 668 } 669 return list_entry(entry, cas_page_t, list); 670} 671 672 673static void cas_mif_poll(struct cas *cp, const int enable) 674{ 675 u32 cfg; 676 677 cfg = readl(cp->regs + REG_MIF_CFG); 678 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1); 679 680 if (cp->phy_type & CAS_PHY_MII_MDIO1) 681 cfg |= MIF_CFG_PHY_SELECT; 682 683 /* poll and interrupt on link status change. */ 684 if (enable) { 685 cfg |= MIF_CFG_POLL_EN; 686 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR); 687 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr); 688 } 689 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, 690 cp->regs + REG_MIF_MASK); 691 writel(cfg, cp->regs + REG_MIF_CFG); 692} 693 694/* Must be invoked under cp->lock */ 695static void cas_begin_auto_negotiation(struct cas *cp, struct ethtool_cmd *ep) 696{ 697 u16 ctl; 698 int lcntl; 699 int changed = 0; 700 int oldstate = cp->lstate; 701 int link_was_not_down = !(oldstate == link_down); 702 /* Setup link parameters */ 703 if (!ep) 704 goto start_aneg; 705 lcntl = cp->link_cntl; 706 if (ep->autoneg == AUTONEG_ENABLE) 707 cp->link_cntl = BMCR_ANENABLE; 708 else { 709 cp->link_cntl = 0; 710 if (ep->speed == SPEED_100) 711 cp->link_cntl |= BMCR_SPEED100; 712 else if (ep->speed == SPEED_1000) 713 cp->link_cntl |= CAS_BMCR_SPEED1000; 714 if (ep->duplex == DUPLEX_FULL) 715 cp->link_cntl |= BMCR_FULLDPLX; 716 } 717 changed = (lcntl != cp->link_cntl); 718start_aneg: 719 if (cp->lstate == link_up) { 720 printk(KERN_INFO "%s: PCS link down.\n", 721 cp->dev->name); 722 } else { 723 if (changed) { 724 printk(KERN_INFO "%s: link configuration changed\n", 725 cp->dev->name); 726 } 727 } 728 cp->lstate = link_down; 729 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 730 if (!cp->hw_running) 731 return; 732 /* 733 * WTZ: If the old state was link_up, we turn off the carrier 734 * to replicate everything we do elsewhere on a link-down 735 * event when we were already in a link-up state.. 736 */ 737 if (oldstate == link_up) 738 netif_carrier_off(cp->dev); 739 if (changed && link_was_not_down) { 740 /* 741 * WTZ: This branch will simply schedule a full reset after 742 * we explicitly changed link modes in an ioctl. See if this 743 * fixes the link-problems we were having for forced mode. 744 */ 745 atomic_inc(&cp->reset_task_pending); 746 atomic_inc(&cp->reset_task_pending_all); 747 schedule_work(&cp->reset_task); 748 cp->timer_ticks = 0; 749 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 750 return; 751 } 752 if (cp->phy_type & CAS_PHY_SERDES) { 753 u32 val = readl(cp->regs + REG_PCS_MII_CTRL); 754 755 if (cp->link_cntl & BMCR_ANENABLE) { 756 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN); 757 cp->lstate = link_aneg; 758 } else { 759 if (cp->link_cntl & BMCR_FULLDPLX) 760 val |= PCS_MII_CTRL_DUPLEX; 761 val &= ~PCS_MII_AUTONEG_EN; 762 cp->lstate = link_force_ok; 763 } 764 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 765 writel(val, cp->regs + REG_PCS_MII_CTRL); 766 767 } else { 768 cas_mif_poll(cp, 0); 769 ctl = cas_phy_read(cp, MII_BMCR); 770 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | 771 CAS_BMCR_SPEED1000 | BMCR_ANENABLE); 772 ctl |= cp->link_cntl; 773 if (ctl & BMCR_ANENABLE) { 774 ctl |= BMCR_ANRESTART; 775 cp->lstate = link_aneg; 776 } else { 777 cp->lstate = link_force_ok; 778 } 779 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 780 cas_phy_write(cp, MII_BMCR, ctl); 781 cas_mif_poll(cp, 1); 782 } 783 784 cp->timer_ticks = 0; 785 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 786} 787 788/* Must be invoked under cp->lock. */ 789static int cas_reset_mii_phy(struct cas *cp) 790{ 791 int limit = STOP_TRIES_PHY; 792 u16 val; 793 794 cas_phy_write(cp, MII_BMCR, BMCR_RESET); 795 udelay(100); 796 while (limit--) { 797 val = cas_phy_read(cp, MII_BMCR); 798 if ((val & BMCR_RESET) == 0) 799 break; 800 udelay(10); 801 } 802 return (limit <= 0); 803} 804 805static void cas_saturn_firmware_load(struct cas *cp) 806{ 807 cas_saturn_patch_t *patch = cas_saturn_patch; 808 809 cas_phy_powerdown(cp); 810 811 /* expanded memory access mode */ 812 cas_phy_write(cp, DP83065_MII_MEM, 0x0); 813 814 /* pointer configuration for new firmware */ 815 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9); 816 cas_phy_write(cp, DP83065_MII_REGD, 0xbd); 817 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa); 818 cas_phy_write(cp, DP83065_MII_REGD, 0x82); 819 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb); 820 cas_phy_write(cp, DP83065_MII_REGD, 0x0); 821 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc); 822 cas_phy_write(cp, DP83065_MII_REGD, 0x39); 823 824 /* download new firmware */ 825 cas_phy_write(cp, DP83065_MII_MEM, 0x1); 826 cas_phy_write(cp, DP83065_MII_REGE, patch->addr); 827 while (patch->addr) { 828 cas_phy_write(cp, DP83065_MII_REGD, patch->val); 829 patch++; 830 } 831 832 /* enable firmware */ 833 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8); 834 cas_phy_write(cp, DP83065_MII_REGD, 0x1); 835} 836 837 838/* phy initialization */ 839static void cas_phy_init(struct cas *cp) 840{ 841 u16 val; 842 843 /* if we're in MII/GMII mode, set up phy */ 844 if (CAS_PHY_MII(cp->phy_type)) { 845 writel(PCS_DATAPATH_MODE_MII, 846 cp->regs + REG_PCS_DATAPATH_MODE); 847 848 cas_mif_poll(cp, 0); 849 cas_reset_mii_phy(cp); /* take out of isolate mode */ 850 851 if (PHY_LUCENT_B0 == cp->phy_id) { 852 cas_phy_write(cp, LUCENT_MII_REG, 0x8000); 853 cas_phy_write(cp, MII_BMCR, 0x00f1); 854 cas_phy_write(cp, LUCENT_MII_REG, 0x0); 855 856 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) { 857 /* workarounds for broadcom phy */ 858 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20); 859 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012); 860 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804); 861 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013); 862 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204); 863 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); 864 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132); 865 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); 866 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232); 867 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F); 868 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20); 869 870 } else if (PHY_BROADCOM_5411 == cp->phy_id) { 871 val = cas_phy_read(cp, BROADCOM_MII_REG4); 872 val = cas_phy_read(cp, BROADCOM_MII_REG4); 873 if (val & 0x0080) { 874 cas_phy_write(cp, BROADCOM_MII_REG4, 875 val & ~0x0080); 876 } 877 878 } else if (cp->cas_flags & CAS_FLAG_SATURN) { 879 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? 880 SATURN_PCFG_FSI : 0x0, 881 cp->regs + REG_SATURN_PCFG); 882 883 /* load firmware to address 10Mbps auto-negotiation 884 * issue. NOTE: this will need to be changed if the 885 * default firmware gets fixed. 886 */ 887 if (PHY_NS_DP83065 == cp->phy_id) { 888 cas_saturn_firmware_load(cp); 889 } 890 cas_phy_powerup(cp); 891 } 892 893 /* advertise capabilities */ 894 val = cas_phy_read(cp, MII_BMCR); 895 val &= ~BMCR_ANENABLE; 896 cas_phy_write(cp, MII_BMCR, val); 897 udelay(10); 898 899 cas_phy_write(cp, MII_ADVERTISE, 900 cas_phy_read(cp, MII_ADVERTISE) | 901 (ADVERTISE_10HALF | ADVERTISE_10FULL | 902 ADVERTISE_100HALF | ADVERTISE_100FULL | 903 CAS_ADVERTISE_PAUSE | 904 CAS_ADVERTISE_ASYM_PAUSE)); 905 906 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 907 /* make sure that we don't advertise half 908 * duplex to avoid a chip issue 909 */ 910 val = cas_phy_read(cp, CAS_MII_1000_CTRL); 911 val &= ~CAS_ADVERTISE_1000HALF; 912 val |= CAS_ADVERTISE_1000FULL; 913 cas_phy_write(cp, CAS_MII_1000_CTRL, val); 914 } 915 916 } else { 917 /* reset pcs for serdes */ 918 u32 val; 919 int limit; 920 921 writel(PCS_DATAPATH_MODE_SERDES, 922 cp->regs + REG_PCS_DATAPATH_MODE); 923 924 /* enable serdes pins on saturn */ 925 if (cp->cas_flags & CAS_FLAG_SATURN) 926 writel(0, cp->regs + REG_SATURN_PCFG); 927 928 /* Reset PCS unit. */ 929 val = readl(cp->regs + REG_PCS_MII_CTRL); 930 val |= PCS_MII_RESET; 931 writel(val, cp->regs + REG_PCS_MII_CTRL); 932 933 limit = STOP_TRIES; 934 while (limit-- > 0) { 935 udelay(10); 936 if ((readl(cp->regs + REG_PCS_MII_CTRL) & 937 PCS_MII_RESET) == 0) 938 break; 939 } 940 if (limit <= 0) 941 printk(KERN_WARNING "%s: PCS reset bit would not " 942 "clear [%08x].\n", cp->dev->name, 943 readl(cp->regs + REG_PCS_STATE_MACHINE)); 944 945 /* Make sure PCS is disabled while changing advertisement 946 * configuration. 947 */ 948 writel(0x0, cp->regs + REG_PCS_CFG); 949 950 /* Advertise all capabilities except half-duplex. */ 951 val = readl(cp->regs + REG_PCS_MII_ADVERT); 952 val &= ~PCS_MII_ADVERT_HD; 953 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE | 954 PCS_MII_ADVERT_ASYM_PAUSE); 955 writel(val, cp->regs + REG_PCS_MII_ADVERT); 956 957 /* enable PCS */ 958 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG); 959 960 writel(PCS_SERDES_CTRL_SYNCD_EN, 961 cp->regs + REG_PCS_SERDES_CTRL); 962 } 963} 964 965 966static int cas_pcs_link_check(struct cas *cp) 967{ 968 u32 stat, state_machine; 969 int retval = 0; 970 971 /* The link status bit latches on zero, so you must 972 * read it twice in such a case to see a transition 973 * to the link being up. 974 */ 975 stat = readl(cp->regs + REG_PCS_MII_STATUS); 976 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0) 977 stat = readl(cp->regs + REG_PCS_MII_STATUS); 978 979 /* The remote-fault indication is only valid 980 * when autoneg has completed. 981 */ 982 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP | 983 PCS_MII_STATUS_REMOTE_FAULT)) == 984 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) { 985 if (netif_msg_link(cp)) 986 printk(KERN_INFO "%s: PCS RemoteFault\n", 987 cp->dev->name); 988 } 989 990 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE); 991 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) { 992 stat &= ~PCS_MII_STATUS_LINK_STATUS; 993 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) { 994 stat |= PCS_MII_STATUS_LINK_STATUS; 995 } 996 997 if (stat & PCS_MII_STATUS_LINK_STATUS) { 998 if (cp->lstate != link_up) { 999 if (cp->opened) { 1000 cp->lstate = link_up; 1001 cp->link_transition = LINK_TRANSITION_LINK_UP; 1002 1003 cas_set_link_modes(cp); 1004 netif_carrier_on(cp->dev); 1005 } 1006 } 1007 } else if (cp->lstate == link_up) { 1008 cp->lstate = link_down; 1009 if (link_transition_timeout != 0 && 1010 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && 1011 !cp->link_transition_jiffies_valid) { 1012 retval = 1; 1013 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; 1014 cp->link_transition_jiffies = jiffies; 1015 cp->link_transition_jiffies_valid = 1; 1016 } else { 1017 cp->link_transition = LINK_TRANSITION_ON_FAILURE; 1018 } 1019 netif_carrier_off(cp->dev); 1020 if (cp->opened && netif_msg_link(cp)) { 1021 printk(KERN_INFO "%s: PCS link down.\n", 1022 cp->dev->name); 1023 } 1024 1025 /* Cassini only: if you force a mode, there can be 1026 * sync problems on link down. to fix that, the following 1027 * things need to be checked: 1028 * 1) read serialink state register 1029 * 2) read pcs status register to verify link down. 1030 * 3) if link down and serial link == 0x03, then you need 1031 * to global reset the chip. 1032 */ 1033 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) { 1034 /* should check to see if we're in a forced mode */ 1035 stat = readl(cp->regs + REG_PCS_SERDES_STATE); 1036 if (stat == 0x03) 1037 return 1; 1038 } 1039 } else if (cp->lstate == link_down) { 1040 if (link_transition_timeout != 0 && 1041 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && 1042 !cp->link_transition_jiffies_valid) { 1043 retval = 1; 1044 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; 1045 cp->link_transition_jiffies = jiffies; 1046 cp->link_transition_jiffies_valid = 1; 1047 } else { 1048 cp->link_transition = LINK_TRANSITION_STILL_FAILED; 1049 } 1050 } 1051 1052 return retval; 1053} 1054 1055static int cas_pcs_interrupt(struct net_device *dev, 1056 struct cas *cp, u32 status) 1057{ 1058 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS); 1059 1060 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0) 1061 return 0; 1062 return cas_pcs_link_check(cp); 1063} 1064 1065static int cas_txmac_interrupt(struct net_device *dev, 1066 struct cas *cp, u32 status) 1067{ 1068 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS); 1069 1070 if (!txmac_stat) 1071 return 0; 1072 1073 if (netif_msg_intr(cp)) 1074 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n", 1075 cp->dev->name, txmac_stat); 1076 1077 /* Defer timer expiration is quite normal, 1078 * don't even log the event. 1079 */ 1080 if ((txmac_stat & MAC_TX_DEFER_TIMER) && 1081 !(txmac_stat & ~MAC_TX_DEFER_TIMER)) 1082 return 0; 1083 1084 spin_lock(&cp->stat_lock[0]); 1085 if (txmac_stat & MAC_TX_UNDERRUN) { 1086 printk(KERN_ERR "%s: TX MAC xmit underrun.\n", 1087 dev->name); 1088 cp->net_stats[0].tx_fifo_errors++; 1089 } 1090 1091 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) { 1092 printk(KERN_ERR "%s: TX MAC max packet size error.\n", 1093 dev->name); 1094 cp->net_stats[0].tx_errors++; 1095 } 1096 1097 /* The rest are all cases of one of the 16-bit TX 1098 * counters expiring. 1099 */ 1100 if (txmac_stat & MAC_TX_COLL_NORMAL) 1101 cp->net_stats[0].collisions += 0x10000; 1102 1103 if (txmac_stat & MAC_TX_COLL_EXCESS) { 1104 cp->net_stats[0].tx_aborted_errors += 0x10000; 1105 cp->net_stats[0].collisions += 0x10000; 1106 } 1107 1108 if (txmac_stat & MAC_TX_COLL_LATE) { 1109 cp->net_stats[0].tx_aborted_errors += 0x10000; 1110 cp->net_stats[0].collisions += 0x10000; 1111 } 1112 spin_unlock(&cp->stat_lock[0]); 1113 1114 /* We do not keep track of MAC_TX_COLL_FIRST and 1115 * MAC_TX_PEAK_ATTEMPTS events. 1116 */ 1117 return 0; 1118} 1119 1120static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware) 1121{ 1122 cas_hp_inst_t *inst; 1123 u32 val; 1124 int i; 1125 1126 i = 0; 1127 while ((inst = firmware) && inst->note) { 1128 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR); 1129 1130 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val); 1131 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask); 1132 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI); 1133 1134 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10); 1135 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop); 1136 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext); 1137 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff); 1138 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext); 1139 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff); 1140 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op); 1141 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID); 1142 1143 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask); 1144 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift); 1145 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab); 1146 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg); 1147 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW); 1148 ++firmware; 1149 ++i; 1150 } 1151} 1152 1153static void cas_init_rx_dma(struct cas *cp) 1154{ 1155 u64 desc_dma = cp->block_dvma; 1156 u32 val; 1157 int i, size; 1158 1159 /* rx free descriptors */ 1160 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL); 1161 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0)); 1162 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0)); 1163 if ((N_RX_DESC_RINGS > 1) && 1164 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */ 1165 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1)); 1166 writel(val, cp->regs + REG_RX_CFG); 1167 1168 val = (unsigned long) cp->init_rxds[0] - 1169 (unsigned long) cp->init_block; 1170 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI); 1171 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW); 1172 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); 1173 1174 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1175 /* rx desc 2 is for IPSEC packets. however, 1176 * we don't it that for that purpose. 1177 */ 1178 val = (unsigned long) cp->init_rxds[1] - 1179 (unsigned long) cp->init_block; 1180 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI); 1181 writel((desc_dma + val) & 0xffffffff, cp->regs + 1182 REG_PLUS_RX_DB1_LOW); 1183 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + 1184 REG_PLUS_RX_KICK1); 1185 } 1186 1187 /* rx completion registers */ 1188 val = (unsigned long) cp->init_rxcs[0] - 1189 (unsigned long) cp->init_block; 1190 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI); 1191 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW); 1192 1193 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1194 /* rx comp 2-4 */ 1195 for (i = 1; i < MAX_RX_COMP_RINGS; i++) { 1196 val = (unsigned long) cp->init_rxcs[i] - 1197 (unsigned long) cp->init_block; 1198 writel((desc_dma + val) >> 32, cp->regs + 1199 REG_PLUS_RX_CBN_HI(i)); 1200 writel((desc_dma + val) & 0xffffffff, cp->regs + 1201 REG_PLUS_RX_CBN_LOW(i)); 1202 } 1203 } 1204 1205 /* read selective clear regs to prevent spurious interrupts 1206 * on reset because complete == kick. 1207 * selective clear set up to prevent interrupts on resets 1208 */ 1209 readl(cp->regs + REG_INTR_STATUS_ALIAS); 1210 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR); 1211 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1212 for (i = 1; i < N_RX_COMP_RINGS; i++) 1213 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i)); 1214 1215 /* 2 is different from 3 and 4 */ 1216 if (N_RX_COMP_RINGS > 1) 1217 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1, 1218 cp->regs + REG_PLUS_ALIASN_CLEAR(1)); 1219 1220 for (i = 2; i < N_RX_COMP_RINGS; i++) 1221 writel(INTR_RX_DONE_ALT, 1222 cp->regs + REG_PLUS_ALIASN_CLEAR(i)); 1223 } 1224 1225 /* set up pause thresholds */ 1226 val = CAS_BASE(RX_PAUSE_THRESH_OFF, 1227 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM); 1228 val |= CAS_BASE(RX_PAUSE_THRESH_ON, 1229 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM); 1230 writel(val, cp->regs + REG_RX_PAUSE_THRESH); 1231 1232 /* zero out dma reassembly buffers */ 1233 for (i = 0; i < 64; i++) { 1234 writel(i, cp->regs + REG_RX_TABLE_ADDR); 1235 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW); 1236 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID); 1237 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI); 1238 } 1239 1240 /* make sure address register is 0 for normal operation */ 1241 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR); 1242 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR); 1243 1244 /* interrupt mitigation */ 1245#ifdef USE_RX_BLANK 1246 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL); 1247 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL); 1248 writel(val, cp->regs + REG_RX_BLANK); 1249#else 1250 writel(0x0, cp->regs + REG_RX_BLANK); 1251#endif 1252 1253 /* interrupt generation as a function of low water marks for 1254 * free desc and completion entries. these are used to trigger 1255 * housekeeping for rx descs. we don't use the free interrupt 1256 * as it's not very useful 1257 */ 1258 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */ 1259 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL); 1260 writel(val, cp->regs + REG_RX_AE_THRESH); 1261 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1262 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1)); 1263 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH); 1264 } 1265 1266 /* Random early detect registers. useful for congestion avoidance. 1267 * this should be tunable. 1268 */ 1269 writel(0x0, cp->regs + REG_RX_RED); 1270 1271 /* receive page sizes. default == 2K (0x800) */ 1272 val = 0; 1273 if (cp->page_size == 0x1000) 1274 val = 0x1; 1275 else if (cp->page_size == 0x2000) 1276 val = 0x2; 1277 else if (cp->page_size == 0x4000) 1278 val = 0x3; 1279 1280 /* round mtu + offset. constrain to page size. */ 1281 size = cp->dev->mtu + 64; 1282 if (size > cp->page_size) 1283 size = cp->page_size; 1284 1285 if (size <= 0x400) 1286 i = 0x0; 1287 else if (size <= 0x800) 1288 i = 0x1; 1289 else if (size <= 0x1000) 1290 i = 0x2; 1291 else 1292 i = 0x3; 1293 1294 cp->mtu_stride = 1 << (i + 10); 1295 val = CAS_BASE(RX_PAGE_SIZE, val); 1296 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i); 1297 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10)); 1298 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1); 1299 writel(val, cp->regs + REG_RX_PAGE_SIZE); 1300 1301 /* enable the header parser if desired */ 1302 if (CAS_HP_FIRMWARE == cas_prog_null) 1303 return; 1304 1305 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS); 1306 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK; 1307 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL); 1308 writel(val, cp->regs + REG_HP_CFG); 1309} 1310 1311static inline void cas_rxc_init(struct cas_rx_comp *rxc) 1312{ 1313 memset(rxc, 0, sizeof(*rxc)); 1314 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO); 1315} 1316 1317/* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1] 1318 * flipping is protected by the fact that the chip will not 1319 * hand back the same page index while it's being processed. 1320 */ 1321static inline cas_page_t *cas_page_spare(struct cas *cp, const int index) 1322{ 1323 cas_page_t *page = cp->rx_pages[1][index]; 1324 cas_page_t *new; 1325 1326 if (cas_buffer_count(page) == 1) 1327 return page; 1328 1329 new = cas_page_dequeue(cp); 1330 if (new) { 1331 spin_lock(&cp->rx_inuse_lock); 1332 list_add(&page->list, &cp->rx_inuse_list); 1333 spin_unlock(&cp->rx_inuse_lock); 1334 } 1335 return new; 1336} 1337 1338/* this needs to be changed if we actually use the ENC RX DESC ring */ 1339static cas_page_t *cas_page_swap(struct cas *cp, const int ring, 1340 const int index) 1341{ 1342 cas_page_t **page0 = cp->rx_pages[0]; 1343 cas_page_t **page1 = cp->rx_pages[1]; 1344 1345 /* swap if buffer is in use */ 1346 if (cas_buffer_count(page0[index]) > 1) { 1347 cas_page_t *new = cas_page_spare(cp, index); 1348 if (new) { 1349 page1[index] = page0[index]; 1350 page0[index] = new; 1351 } 1352 } 1353 RX_USED_SET(page0[index], 0); 1354 return page0[index]; 1355} 1356 1357static void cas_clean_rxds(struct cas *cp) 1358{ 1359 /* only clean ring 0 as ring 1 is used for spare buffers */ 1360 struct cas_rx_desc *rxd = cp->init_rxds[0]; 1361 int i, size; 1362 1363 /* release all rx flows */ 1364 for (i = 0; i < N_RX_FLOWS; i++) { 1365 struct sk_buff *skb; 1366 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) { 1367 cas_skb_release(skb); 1368 } 1369 } 1370 1371 /* initialize descriptors */ 1372 size = RX_DESC_RINGN_SIZE(0); 1373 for (i = 0; i < size; i++) { 1374 cas_page_t *page = cas_page_swap(cp, 0, i); 1375 rxd[i].buffer = cpu_to_le64(page->dma_addr); 1376 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) | 1377 CAS_BASE(RX_INDEX_RING, 0)); 1378 } 1379 1380 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4; 1381 cp->rx_last[0] = 0; 1382 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0); 1383} 1384 1385static void cas_clean_rxcs(struct cas *cp) 1386{ 1387 int i, j; 1388 1389 /* take ownership of rx comp descriptors */ 1390 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS); 1391 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS); 1392 for (i = 0; i < N_RX_COMP_RINGS; i++) { 1393 struct cas_rx_comp *rxc = cp->init_rxcs[i]; 1394 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) { 1395 cas_rxc_init(rxc + j); 1396 } 1397 } 1398} 1399 1400 1401static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp, 1402 u32 status) 1403{ 1404 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS); 1405 1406 if (!stat) 1407 return 0; 1408 1409 if (netif_msg_intr(cp)) 1410 printk(KERN_DEBUG "%s: rxmac interrupt, stat: 0x%x\n", 1411 cp->dev->name, stat); 1412 1413 /* these are all rollovers */ 1414 spin_lock(&cp->stat_lock[0]); 1415 if (stat & MAC_RX_ALIGN_ERR) 1416 cp->net_stats[0].rx_frame_errors += 0x10000; 1417 1418 if (stat & MAC_RX_CRC_ERR) 1419 cp->net_stats[0].rx_crc_errors += 0x10000; 1420 1421 if (stat & MAC_RX_LEN_ERR) 1422 cp->net_stats[0].rx_length_errors += 0x10000; 1423 1424 if (stat & MAC_RX_OVERFLOW) { 1425 cp->net_stats[0].rx_over_errors++; 1426 cp->net_stats[0].rx_fifo_errors++; 1427 } 1428 1429 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR 1430 * events. 1431 */ 1432 spin_unlock(&cp->stat_lock[0]); 1433 return 0; 1434} 1435 1436static int cas_mac_interrupt(struct net_device *dev, struct cas *cp, 1437 u32 status) 1438{ 1439 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS); 1440 1441 if (!stat) 1442 return 0; 1443 1444 if (netif_msg_intr(cp)) 1445 printk(KERN_DEBUG "%s: mac interrupt, stat: 0x%x\n", 1446 cp->dev->name, stat); 1447 1448 /* This interrupt is just for pause frame and pause 1449 * tracking. It is useful for diagnostics and debug 1450 * but probably by default we will mask these events. 1451 */ 1452 if (stat & MAC_CTRL_PAUSE_STATE) 1453 cp->pause_entered++; 1454 1455 if (stat & MAC_CTRL_PAUSE_RECEIVED) 1456 cp->pause_last_time_recvd = (stat >> 16); 1457 1458 return 0; 1459} 1460 1461 1462/* Must be invoked under cp->lock. */ 1463static inline int cas_mdio_link_not_up(struct cas *cp) 1464{ 1465 u16 val; 1466 1467 switch (cp->lstate) { 1468 case link_force_ret: 1469 if (netif_msg_link(cp)) 1470 printk(KERN_INFO "%s: Autoneg failed again, keeping" 1471 " forced mode\n", cp->dev->name); 1472 cas_phy_write(cp, MII_BMCR, cp->link_fcntl); 1473 cp->timer_ticks = 5; 1474 cp->lstate = link_force_ok; 1475 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1476 break; 1477 1478 case link_aneg: 1479 val = cas_phy_read(cp, MII_BMCR); 1480 1481 /* Try forced modes. we try things in the following order: 1482 * 1000 full -> 100 full/half -> 10 half 1483 */ 1484 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE); 1485 val |= BMCR_FULLDPLX; 1486 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 1487 CAS_BMCR_SPEED1000 : BMCR_SPEED100; 1488 cas_phy_write(cp, MII_BMCR, val); 1489 cp->timer_ticks = 5; 1490 cp->lstate = link_force_try; 1491 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1492 break; 1493 1494 case link_force_try: 1495 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */ 1496 val = cas_phy_read(cp, MII_BMCR); 1497 cp->timer_ticks = 5; 1498 if (val & CAS_BMCR_SPEED1000) { /* gigabit */ 1499 val &= ~CAS_BMCR_SPEED1000; 1500 val |= (BMCR_SPEED100 | BMCR_FULLDPLX); 1501 cas_phy_write(cp, MII_BMCR, val); 1502 break; 1503 } 1504 1505 if (val & BMCR_SPEED100) { 1506 if (val & BMCR_FULLDPLX) /* fd failed */ 1507 val &= ~BMCR_FULLDPLX; 1508 else { /* 100Mbps failed */ 1509 val &= ~BMCR_SPEED100; 1510 } 1511 cas_phy_write(cp, MII_BMCR, val); 1512 break; 1513 } 1514 default: 1515 break; 1516 } 1517 return 0; 1518} 1519 1520 1521/* must be invoked with cp->lock held */ 1522static int cas_mii_link_check(struct cas *cp, const u16 bmsr) 1523{ 1524 int restart; 1525 1526 if (bmsr & BMSR_LSTATUS) { 1527 /* Ok, here we got a link. If we had it due to a forced 1528 * fallback, and we were configured for autoneg, we 1529 * retry a short autoneg pass. If you know your hub is 1530 * broken, use ethtool ;) 1531 */ 1532 if ((cp->lstate == link_force_try) && 1533 (cp->link_cntl & BMCR_ANENABLE)) { 1534 cp->lstate = link_force_ret; 1535 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1536 cas_mif_poll(cp, 0); 1537 cp->link_fcntl = cas_phy_read(cp, MII_BMCR); 1538 cp->timer_ticks = 5; 1539 if (cp->opened && netif_msg_link(cp)) 1540 printk(KERN_INFO "%s: Got link after fallback, retrying" 1541 " autoneg once...\n", cp->dev->name); 1542 cas_phy_write(cp, MII_BMCR, 1543 cp->link_fcntl | BMCR_ANENABLE | 1544 BMCR_ANRESTART); 1545 cas_mif_poll(cp, 1); 1546 1547 } else if (cp->lstate != link_up) { 1548 cp->lstate = link_up; 1549 cp->link_transition = LINK_TRANSITION_LINK_UP; 1550 1551 if (cp->opened) { 1552 cas_set_link_modes(cp); 1553 netif_carrier_on(cp->dev); 1554 } 1555 } 1556 return 0; 1557 } 1558 1559 /* link not up. if the link was previously up, we restart the 1560 * whole process 1561 */ 1562 restart = 0; 1563 if (cp->lstate == link_up) { 1564 cp->lstate = link_down; 1565 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 1566 1567 netif_carrier_off(cp->dev); 1568 if (cp->opened && netif_msg_link(cp)) 1569 printk(KERN_INFO "%s: Link down\n", 1570 cp->dev->name); 1571 restart = 1; 1572 1573 } else if (++cp->timer_ticks > 10) 1574 cas_mdio_link_not_up(cp); 1575 1576 return restart; 1577} 1578 1579static int cas_mif_interrupt(struct net_device *dev, struct cas *cp, 1580 u32 status) 1581{ 1582 u32 stat = readl(cp->regs + REG_MIF_STATUS); 1583 u16 bmsr; 1584 1585 /* check for a link change */ 1586 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0) 1587 return 0; 1588 1589 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat); 1590 return cas_mii_link_check(cp, bmsr); 1591} 1592 1593static int cas_pci_interrupt(struct net_device *dev, struct cas *cp, 1594 u32 status) 1595{ 1596 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS); 1597 1598 if (!stat) 1599 return 0; 1600 1601 printk(KERN_ERR "%s: PCI error [%04x:%04x] ", dev->name, stat, 1602 readl(cp->regs + REG_BIM_DIAG)); 1603 1604 /* cassini+ has this reserved */ 1605 if ((stat & PCI_ERR_BADACK) && 1606 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0)) 1607 printk("<No ACK64# during ABS64 cycle> "); 1608 1609 if (stat & PCI_ERR_DTRTO) 1610 printk("<Delayed transaction timeout> "); 1611 if (stat & PCI_ERR_OTHER) 1612 printk("<other> "); 1613 if (stat & PCI_ERR_BIM_DMA_WRITE) 1614 printk("<BIM DMA 0 write req> "); 1615 if (stat & PCI_ERR_BIM_DMA_READ) 1616 printk("<BIM DMA 0 read req> "); 1617 printk("\n"); 1618 1619 if (stat & PCI_ERR_OTHER) { 1620 u16 cfg; 1621 1622 /* Interrogate PCI config space for the 1623 * true cause. 1624 */ 1625 pci_read_config_word(cp->pdev, PCI_STATUS, &cfg); 1626 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n", 1627 dev->name, cfg); 1628 if (cfg & PCI_STATUS_PARITY) 1629 printk(KERN_ERR "%s: PCI parity error detected.\n", 1630 dev->name); 1631 if (cfg & PCI_STATUS_SIG_TARGET_ABORT) 1632 printk(KERN_ERR "%s: PCI target abort.\n", 1633 dev->name); 1634 if (cfg & PCI_STATUS_REC_TARGET_ABORT) 1635 printk(KERN_ERR "%s: PCI master acks target abort.\n", 1636 dev->name); 1637 if (cfg & PCI_STATUS_REC_MASTER_ABORT) 1638 printk(KERN_ERR "%s: PCI master abort.\n", dev->name); 1639 if (cfg & PCI_STATUS_SIG_SYSTEM_ERROR) 1640 printk(KERN_ERR "%s: PCI system error SERR#.\n", 1641 dev->name); 1642 if (cfg & PCI_STATUS_DETECTED_PARITY) 1643 printk(KERN_ERR "%s: PCI parity error.\n", 1644 dev->name); 1645 1646 /* Write the error bits back to clear them. */ 1647 cfg &= (PCI_STATUS_PARITY | 1648 PCI_STATUS_SIG_TARGET_ABORT | 1649 PCI_STATUS_REC_TARGET_ABORT | 1650 PCI_STATUS_REC_MASTER_ABORT | 1651 PCI_STATUS_SIG_SYSTEM_ERROR | 1652 PCI_STATUS_DETECTED_PARITY); 1653 pci_write_config_word(cp->pdev, PCI_STATUS, cfg); 1654 } 1655 1656 /* For all PCI errors, we should reset the chip. */ 1657 return 1; 1658} 1659 1660/* All non-normal interrupt conditions get serviced here. 1661 * Returns non-zero if we should just exit the interrupt 1662 * handler right now (ie. if we reset the card which invalidates 1663 * all of the other original irq status bits). 1664 */ 1665static int cas_abnormal_irq(struct net_device *dev, struct cas *cp, 1666 u32 status) 1667{ 1668 if (status & INTR_RX_TAG_ERROR) { 1669 /* corrupt RX tag framing */ 1670 if (netif_msg_rx_err(cp)) 1671 printk(KERN_DEBUG "%s: corrupt rx tag framing\n", 1672 cp->dev->name); 1673 spin_lock(&cp->stat_lock[0]); 1674 cp->net_stats[0].rx_errors++; 1675 spin_unlock(&cp->stat_lock[0]); 1676 goto do_reset; 1677 } 1678 1679 if (status & INTR_RX_LEN_MISMATCH) { 1680 /* length mismatch. */ 1681 if (netif_msg_rx_err(cp)) 1682 printk(KERN_DEBUG "%s: length mismatch for rx frame\n", 1683 cp->dev->name); 1684 spin_lock(&cp->stat_lock[0]); 1685 cp->net_stats[0].rx_errors++; 1686 spin_unlock(&cp->stat_lock[0]); 1687 goto do_reset; 1688 } 1689 1690 if (status & INTR_PCS_STATUS) { 1691 if (cas_pcs_interrupt(dev, cp, status)) 1692 goto do_reset; 1693 } 1694 1695 if (status & INTR_TX_MAC_STATUS) { 1696 if (cas_txmac_interrupt(dev, cp, status)) 1697 goto do_reset; 1698 } 1699 1700 if (status & INTR_RX_MAC_STATUS) { 1701 if (cas_rxmac_interrupt(dev, cp, status)) 1702 goto do_reset; 1703 } 1704 1705 if (status & INTR_MAC_CTRL_STATUS) { 1706 if (cas_mac_interrupt(dev, cp, status)) 1707 goto do_reset; 1708 } 1709 1710 if (status & INTR_MIF_STATUS) { 1711 if (cas_mif_interrupt(dev, cp, status)) 1712 goto do_reset; 1713 } 1714 1715 if (status & INTR_PCI_ERROR_STATUS) { 1716 if (cas_pci_interrupt(dev, cp, status)) 1717 goto do_reset; 1718 } 1719 return 0; 1720 1721do_reset: 1722 atomic_inc(&cp->reset_task_pending); 1723 atomic_inc(&cp->reset_task_pending_all); 1724 printk(KERN_ERR "%s:reset called in cas_abnormal_irq [0x%x]\n", 1725 dev->name, status); 1726 schedule_work(&cp->reset_task); 1727 return 1; 1728} 1729 1730/* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when 1731 * determining whether to do a netif_stop/wakeup 1732 */ 1733#define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1) 1734#define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK) 1735static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr, 1736 const int len) 1737{ 1738 unsigned long off = addr + len; 1739 1740 if (CAS_TABORT(cp) == 1) 1741 return 0; 1742 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN) 1743 return 0; 1744 return TX_TARGET_ABORT_LEN; 1745} 1746 1747static inline void cas_tx_ringN(struct cas *cp, int ring, int limit) 1748{ 1749 struct cas_tx_desc *txds; 1750 struct sk_buff **skbs; 1751 struct net_device *dev = cp->dev; 1752 int entry, count; 1753 1754 spin_lock(&cp->tx_lock[ring]); 1755 txds = cp->init_txds[ring]; 1756 skbs = cp->tx_skbs[ring]; 1757 entry = cp->tx_old[ring]; 1758 1759 count = TX_BUFF_COUNT(ring, entry, limit); 1760 while (entry != limit) { 1761 struct sk_buff *skb = skbs[entry]; 1762 dma_addr_t daddr; 1763 u32 dlen; 1764 int frag; 1765 1766 if (!skb) { 1767 /* this should never occur */ 1768 entry = TX_DESC_NEXT(ring, entry); 1769 continue; 1770 } 1771 1772 /* however, we might get only a partial skb release. */ 1773 count -= skb_shinfo(skb)->nr_frags + 1774 + cp->tx_tiny_use[ring][entry].nbufs + 1; 1775 if (count < 0) 1776 break; 1777 1778 if (netif_msg_tx_done(cp)) 1779 printk(KERN_DEBUG "%s: tx[%d] done, slot %d\n", 1780 cp->dev->name, ring, entry); 1781 1782 skbs[entry] = NULL; 1783 cp->tx_tiny_use[ring][entry].nbufs = 0; 1784 1785 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1786 struct cas_tx_desc *txd = txds + entry; 1787 1788 daddr = le64_to_cpu(txd->buffer); 1789 dlen = CAS_VAL(TX_DESC_BUFLEN, 1790 le64_to_cpu(txd->control)); 1791 pci_unmap_page(cp->pdev, daddr, dlen, 1792 PCI_DMA_TODEVICE); 1793 entry = TX_DESC_NEXT(ring, entry); 1794 1795 /* tiny buffer may follow */ 1796 if (cp->tx_tiny_use[ring][entry].used) { 1797 cp->tx_tiny_use[ring][entry].used = 0; 1798 entry = TX_DESC_NEXT(ring, entry); 1799 } 1800 } 1801 1802 spin_lock(&cp->stat_lock[ring]); 1803 cp->net_stats[ring].tx_packets++; 1804 cp->net_stats[ring].tx_bytes += skb->len; 1805 spin_unlock(&cp->stat_lock[ring]); 1806 dev_kfree_skb_irq(skb); 1807 } 1808 cp->tx_old[ring] = entry; 1809 1810 /* this is wrong for multiple tx rings. the net device needs 1811 * multiple queues for this to do the right thing. we wait 1812 * for 2*packets to be available when using tiny buffers 1813 */ 1814 if (netif_queue_stopped(dev) && 1815 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))) 1816 netif_wake_queue(dev); 1817 spin_unlock(&cp->tx_lock[ring]); 1818} 1819 1820static void cas_tx(struct net_device *dev, struct cas *cp, 1821 u32 status) 1822{ 1823 int limit, ring; 1824#ifdef USE_TX_COMPWB 1825 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb); 1826#endif 1827 if (netif_msg_intr(cp)) 1828 printk(KERN_DEBUG "%s: tx interrupt, status: 0x%x, %llx\n", 1829 cp->dev->name, status, (unsigned long long)compwb); 1830 /* process all the rings */ 1831 for (ring = 0; ring < N_TX_RINGS; ring++) { 1832#ifdef USE_TX_COMPWB 1833 /* use the completion writeback registers */ 1834 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) | 1835 CAS_VAL(TX_COMPWB_LSB, compwb); 1836 compwb = TX_COMPWB_NEXT(compwb); 1837#else 1838 limit = readl(cp->regs + REG_TX_COMPN(ring)); 1839#endif 1840 if (cp->tx_old[ring] != limit) 1841 cas_tx_ringN(cp, ring, limit); 1842 } 1843} 1844 1845 1846static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc, 1847 int entry, const u64 *words, 1848 struct sk_buff **skbref) 1849{ 1850 int dlen, hlen, len, i, alloclen; 1851 int off, swivel = RX_SWIVEL_OFF_VAL; 1852 struct cas_page *page; 1853 struct sk_buff *skb; 1854 void *addr, *crcaddr; 1855 char *p; 1856 1857 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]); 1858 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]); 1859 len = hlen + dlen; 1860 1861 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT)) 1862 alloclen = len; 1863 else 1864 alloclen = max(hlen, RX_COPY_MIN); 1865 1866 skb = dev_alloc_skb(alloclen + swivel + cp->crc_size); 1867 if (skb == NULL) 1868 return -1; 1869 1870 *skbref = skb; 1871 skb_reserve(skb, swivel); 1872 1873 p = skb->data; 1874 addr = crcaddr = NULL; 1875 if (hlen) { /* always copy header pages */ 1876 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); 1877 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1878 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 + 1879 swivel; 1880 1881 i = hlen; 1882 if (!dlen) /* attach FCS */ 1883 i += cp->crc_size; 1884 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i, 1885 PCI_DMA_FROMDEVICE); 1886 addr = cas_page_map(page->buffer); 1887 memcpy(p, addr + off, i); 1888 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i, 1889 PCI_DMA_FROMDEVICE); 1890 cas_page_unmap(addr); 1891 RX_USED_ADD(page, 0x100); 1892 p += hlen; 1893 swivel = 0; 1894 } 1895 1896 1897 if (alloclen < (hlen + dlen)) { 1898 skb_frag_t *frag = skb_shinfo(skb)->frags; 1899 1900 /* normal or jumbo packets. we use frags */ 1901 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 1902 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1903 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; 1904 1905 hlen = min(cp->page_size - off, dlen); 1906 if (hlen < 0) { 1907 if (netif_msg_rx_err(cp)) { 1908 printk(KERN_DEBUG "%s: rx page overflow: " 1909 "%d\n", cp->dev->name, hlen); 1910 } 1911 dev_kfree_skb_irq(skb); 1912 return -1; 1913 } 1914 i = hlen; 1915 if (i == dlen) /* attach FCS */ 1916 i += cp->crc_size; 1917 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i, 1918 PCI_DMA_FROMDEVICE); 1919 1920 /* make sure we always copy a header */ 1921 swivel = 0; 1922 if (p == (char *) skb->data) { /* not split */ 1923 addr = cas_page_map(page->buffer); 1924 memcpy(p, addr + off, RX_COPY_MIN); 1925 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i, 1926 PCI_DMA_FROMDEVICE); 1927 cas_page_unmap(addr); 1928 off += RX_COPY_MIN; 1929 swivel = RX_COPY_MIN; 1930 RX_USED_ADD(page, cp->mtu_stride); 1931 } else { 1932 RX_USED_ADD(page, hlen); 1933 } 1934 skb_put(skb, alloclen); 1935 1936 skb_shinfo(skb)->nr_frags++; 1937 skb->data_len += hlen - swivel; 1938 skb->len += hlen - swivel; 1939 1940 get_page(page->buffer); 1941 cas_buffer_inc(page); 1942 frag->page = page->buffer; 1943 frag->page_offset = off; 1944 frag->size = hlen - swivel; 1945 1946 /* any more data? */ 1947 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { 1948 hlen = dlen; 1949 off = 0; 1950 1951 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 1952 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1953 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, 1954 hlen + cp->crc_size, 1955 PCI_DMA_FROMDEVICE); 1956 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr, 1957 hlen + cp->crc_size, 1958 PCI_DMA_FROMDEVICE); 1959 1960 skb_shinfo(skb)->nr_frags++; 1961 skb->data_len += hlen; 1962 skb->len += hlen; 1963 frag++; 1964 1965 get_page(page->buffer); 1966 cas_buffer_inc(page); 1967 frag->page = page->buffer; 1968 frag->page_offset = 0; 1969 frag->size = hlen; 1970 RX_USED_ADD(page, hlen + cp->crc_size); 1971 } 1972 1973 if (cp->crc_size) { 1974 addr = cas_page_map(page->buffer); 1975 crcaddr = addr + off + hlen; 1976 } 1977 1978 } else { 1979 /* copying packet */ 1980 if (!dlen) 1981 goto end_copy_pkt; 1982 1983 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 1984 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1985 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; 1986 hlen = min(cp->page_size - off, dlen); 1987 if (hlen < 0) { 1988 if (netif_msg_rx_err(cp)) { 1989 printk(KERN_DEBUG "%s: rx page overflow: " 1990 "%d\n", cp->dev->name, hlen); 1991 } 1992 dev_kfree_skb_irq(skb); 1993 return -1; 1994 } 1995 i = hlen; 1996 if (i == dlen) /* attach FCS */ 1997 i += cp->crc_size; 1998 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr + off, i, 1999 PCI_DMA_FROMDEVICE); 2000 addr = cas_page_map(page->buffer); 2001 memcpy(p, addr + off, i); 2002 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr + off, i, 2003 PCI_DMA_FROMDEVICE); 2004 cas_page_unmap(addr); 2005 if (p == (char *) skb->data) /* not split */ 2006 RX_USED_ADD(page, cp->mtu_stride); 2007 else 2008 RX_USED_ADD(page, i); 2009 2010 /* any more data? */ 2011 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { 2012 p += hlen; 2013 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2014 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 2015 pci_dma_sync_single_for_cpu(cp->pdev, page->dma_addr, 2016 dlen + cp->crc_size, 2017 PCI_DMA_FROMDEVICE); 2018 addr = cas_page_map(page->buffer); 2019 memcpy(p, addr, dlen + cp->crc_size); 2020 pci_dma_sync_single_for_device(cp->pdev, page->dma_addr, 2021 dlen + cp->crc_size, 2022 PCI_DMA_FROMDEVICE); 2023 cas_page_unmap(addr); 2024 RX_USED_ADD(page, dlen + cp->crc_size); 2025 } 2026end_copy_pkt: 2027 if (cp->crc_size) { 2028 addr = NULL; 2029 crcaddr = skb->data + alloclen; 2030 } 2031 skb_put(skb, alloclen); 2032 } 2033 2034 i = CAS_VAL(RX_COMP4_TCP_CSUM, words[3]); 2035 if (cp->crc_size) { 2036 /* checksum includes FCS. strip it out. */ 2037 i = csum_fold(csum_partial(crcaddr, cp->crc_size, i)); 2038 if (addr) 2039 cas_page_unmap(addr); 2040 } 2041 skb->csum = ntohs(i ^ 0xffff); 2042 skb->ip_summed = CHECKSUM_COMPLETE; 2043 skb->protocol = eth_type_trans(skb, cp->dev); 2044 return len; 2045} 2046 2047 2048/* we can handle up to 64 rx flows at a time. we do the same thing 2049 * as nonreassm except that we batch up the buffers. 2050 * NOTE: we currently just treat each flow as a bunch of packets that 2051 * we pass up. a better way would be to coalesce the packets 2052 * into a jumbo packet. to do that, we need to do the following: 2053 * 1) the first packet will have a clean split between header and 2054 * data. save both. 2055 * 2) each time the next flow packet comes in, extend the 2056 * data length and merge the checksums. 2057 * 3) on flow release, fix up the header. 2058 * 4) make sure the higher layer doesn't care. 2059 * because packets get coalesced, we shouldn't run into fragment count 2060 * issues. 2061 */ 2062static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words, 2063 struct sk_buff *skb) 2064{ 2065 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1); 2066 struct sk_buff_head *flow = &cp->rx_flows[flowid]; 2067 2068 /* this is protected at a higher layer, so no need to 2069 * do any additional locking here. stick the buffer 2070 * at the end. 2071 */ 2072 __skb_insert(skb, flow->prev, (struct sk_buff *) flow, flow); 2073 if (words[0] & RX_COMP1_RELEASE_FLOW) { 2074 while ((skb = __skb_dequeue(flow))) { 2075 cas_skb_release(skb); 2076 } 2077 } 2078} 2079 2080/* put rx descriptor back on ring. if a buffer is in use by a higher 2081 * layer, this will need to put in a replacement. 2082 */ 2083static void cas_post_page(struct cas *cp, const int ring, const int index) 2084{ 2085 cas_page_t *new; 2086 int entry; 2087 2088 entry = cp->rx_old[ring]; 2089 2090 new = cas_page_swap(cp, ring, index); 2091 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr); 2092 cp->init_rxds[ring][entry].index = 2093 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) | 2094 CAS_BASE(RX_INDEX_RING, ring)); 2095 2096 entry = RX_DESC_ENTRY(ring, entry + 1); 2097 cp->rx_old[ring] = entry; 2098 2099 if (entry % 4) 2100 return; 2101 2102 if (ring == 0) 2103 writel(entry, cp->regs + REG_RX_KICK); 2104 else if ((N_RX_DESC_RINGS > 1) && 2105 (cp->cas_flags & CAS_FLAG_REG_PLUS)) 2106 writel(entry, cp->regs + REG_PLUS_RX_KICK1); 2107} 2108 2109 2110/* only when things are bad */ 2111static int cas_post_rxds_ringN(struct cas *cp, int ring, int num) 2112{ 2113 unsigned int entry, last, count, released; 2114 int cluster; 2115 cas_page_t **page = cp->rx_pages[ring]; 2116 2117 entry = cp->rx_old[ring]; 2118 2119 if (netif_msg_intr(cp)) 2120 printk(KERN_DEBUG "%s: rxd[%d] interrupt, done: %d\n", 2121 cp->dev->name, ring, entry); 2122 2123 cluster = -1; 2124 count = entry & 0x3; 2125 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4); 2126 released = 0; 2127 while (entry != last) { 2128 /* make a new buffer if it's still in use */ 2129 if (cas_buffer_count(page[entry]) > 1) { 2130 cas_page_t *new = cas_page_dequeue(cp); 2131 if (!new) { 2132 /* let the timer know that we need to 2133 * do this again 2134 */ 2135 cp->cas_flags |= CAS_FLAG_RXD_POST(ring); 2136 if (!timer_pending(&cp->link_timer)) 2137 mod_timer(&cp->link_timer, jiffies + 2138 CAS_LINK_FAST_TIMEOUT); 2139 cp->rx_old[ring] = entry; 2140 cp->rx_last[ring] = num ? num - released : 0; 2141 return -ENOMEM; 2142 } 2143 spin_lock(&cp->rx_inuse_lock); 2144 list_add(&page[entry]->list, &cp->rx_inuse_list); 2145 spin_unlock(&cp->rx_inuse_lock); 2146 cp->init_rxds[ring][entry].buffer = 2147 cpu_to_le64(new->dma_addr); 2148 page[entry] = new; 2149 2150 } 2151 2152 if (++count == 4) { 2153 cluster = entry; 2154 count = 0; 2155 } 2156 released++; 2157 entry = RX_DESC_ENTRY(ring, entry + 1); 2158 } 2159 cp->rx_old[ring] = entry; 2160 2161 if (cluster < 0) 2162 return 0; 2163 2164 if (ring == 0) 2165 writel(cluster, cp->regs + REG_RX_KICK); 2166 else if ((N_RX_DESC_RINGS > 1) && 2167 (cp->cas_flags & CAS_FLAG_REG_PLUS)) 2168 writel(cluster, cp->regs + REG_PLUS_RX_KICK1); 2169 return 0; 2170} 2171 2172 2173/* process a completion ring. packets are set up in three basic ways: 2174 * small packets: should be copied header + data in single buffer. 2175 * large packets: header and data in a single buffer. 2176 * split packets: header in a separate buffer from data. 2177 * data may be in multiple pages. data may be > 256 2178 * bytes but in a single page. 2179 * 2180 * NOTE: RX page posting is done in this routine as well. while there's 2181 * the capability of using multiple RX completion rings, it isn't 2182 * really worthwhile due to the fact that the page posting will 2183 * force serialization on the single descriptor ring. 2184 */ 2185static int cas_rx_ringN(struct cas *cp, int ring, int budget) 2186{ 2187 struct cas_rx_comp *rxcs = cp->init_rxcs[ring]; 2188 int entry, drops; 2189 int npackets = 0; 2190 2191 if (netif_msg_intr(cp)) 2192 printk(KERN_DEBUG "%s: rx[%d] interrupt, done: %d/%d\n", 2193 cp->dev->name, ring, 2194 readl(cp->regs + REG_RX_COMP_HEAD), 2195 cp->rx_new[ring]); 2196 2197 entry = cp->rx_new[ring]; 2198 drops = 0; 2199 while (1) { 2200 struct cas_rx_comp *rxc = rxcs + entry; 2201 struct sk_buff *skb; 2202 int type, len; 2203 u64 words[4]; 2204 int i, dring; 2205 2206 words[0] = le64_to_cpu(rxc->word1); 2207 words[1] = le64_to_cpu(rxc->word2); 2208 words[2] = le64_to_cpu(rxc->word3); 2209 words[3] = le64_to_cpu(rxc->word4); 2210 2211 /* don't touch if still owned by hw */ 2212 type = CAS_VAL(RX_COMP1_TYPE, words[0]); 2213 if (type == 0) 2214 break; 2215 2216 /* hw hasn't cleared the zero bit yet */ 2217 if (words[3] & RX_COMP4_ZERO) { 2218 break; 2219 } 2220 2221 /* get info on the packet */ 2222 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) { 2223 spin_lock(&cp->stat_lock[ring]); 2224 cp->net_stats[ring].rx_errors++; 2225 if (words[3] & RX_COMP4_LEN_MISMATCH) 2226 cp->net_stats[ring].rx_length_errors++; 2227 if (words[3] & RX_COMP4_BAD) 2228 cp->net_stats[ring].rx_crc_errors++; 2229 spin_unlock(&cp->stat_lock[ring]); 2230 2231 /* We'll just return it to Cassini. */ 2232 drop_it: 2233 spin_lock(&cp->stat_lock[ring]); 2234 ++cp->net_stats[ring].rx_dropped; 2235 spin_unlock(&cp->stat_lock[ring]); 2236 goto next; 2237 } 2238 2239 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb); 2240 if (len < 0) { 2241 ++drops; 2242 goto drop_it; 2243 } 2244 2245 /* see if it's a flow re-assembly or not. the driver 2246 * itself handles release back up. 2247 */ 2248 if (RX_DONT_BATCH || (type == 0x2)) { 2249 /* non-reassm: these always get released */ 2250 cas_skb_release(skb); 2251 } else { 2252 cas_rx_flow_pkt(cp, words, skb); 2253 } 2254 2255 spin_lock(&cp->stat_lock[ring]); 2256 cp->net_stats[ring].rx_packets++; 2257 cp->net_stats[ring].rx_bytes += len; 2258 spin_unlock(&cp->stat_lock[ring]); 2259 cp->dev->last_rx = jiffies; 2260 2261 next: 2262 npackets++; 2263 2264 /* should it be released? */ 2265 if (words[0] & RX_COMP1_RELEASE_HDR) { 2266 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); 2267 dring = CAS_VAL(RX_INDEX_RING, i); 2268 i = CAS_VAL(RX_INDEX_NUM, i); 2269 cas_post_page(cp, dring, i); 2270 } 2271 2272 if (words[0] & RX_COMP1_RELEASE_DATA) { 2273 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 2274 dring = CAS_VAL(RX_INDEX_RING, i); 2275 i = CAS_VAL(RX_INDEX_NUM, i); 2276 cas_post_page(cp, dring, i); 2277 } 2278 2279 if (words[0] & RX_COMP1_RELEASE_NEXT) { 2280 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2281 dring = CAS_VAL(RX_INDEX_RING, i); 2282 i = CAS_VAL(RX_INDEX_NUM, i); 2283 cas_post_page(cp, dring, i); 2284 } 2285 2286 /* skip to the next entry */ 2287 entry = RX_COMP_ENTRY(ring, entry + 1 + 2288 CAS_VAL(RX_COMP1_SKIP, words[0])); 2289#ifdef USE_NAPI 2290 if (budget && (npackets >= budget)) 2291 break; 2292#endif 2293 } 2294 cp->rx_new[ring] = entry; 2295 2296 if (drops) 2297 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", 2298 cp->dev->name); 2299 return npackets; 2300} 2301 2302 2303/* put completion entries back on the ring */ 2304static void cas_post_rxcs_ringN(struct net_device *dev, 2305 struct cas *cp, int ring) 2306{ 2307 struct cas_rx_comp *rxc = cp->init_rxcs[ring]; 2308 int last, entry; 2309 2310 last = cp->rx_cur[ring]; 2311 entry = cp->rx_new[ring]; 2312 if (netif_msg_intr(cp)) 2313 printk(KERN_DEBUG "%s: rxc[%d] interrupt, done: %d/%d\n", 2314 dev->name, ring, readl(cp->regs + REG_RX_COMP_HEAD), 2315 entry); 2316 2317 /* zero and re-mark descriptors */ 2318 while (last != entry) { 2319 cas_rxc_init(rxc + last); 2320 last = RX_COMP_ENTRY(ring, last + 1); 2321 } 2322 cp->rx_cur[ring] = last; 2323 2324 if (ring == 0) 2325 writel(last, cp->regs + REG_RX_COMP_TAIL); 2326 else if (cp->cas_flags & CAS_FLAG_REG_PLUS) 2327 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring)); 2328} 2329 2330 2331 2332/* cassini can use all four PCI interrupts for the completion ring. 2333 * rings 3 and 4 are identical 2334 */ 2335#if defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 2336static inline void cas_handle_irqN(struct net_device *dev, 2337 struct cas *cp, const u32 status, 2338 const int ring) 2339{ 2340 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT)) 2341 cas_post_rxcs_ringN(dev, cp, ring); 2342} 2343 2344static irqreturn_t cas_interruptN(int irq, void *dev_id) 2345{ 2346 struct net_device *dev = dev_id; 2347 struct cas *cp = netdev_priv(dev); 2348 unsigned long flags; 2349 int ring; 2350 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); 2351 2352 /* check for shared irq */ 2353 if (status == 0) 2354 return IRQ_NONE; 2355 2356 ring = (irq == cp->pci_irq_INTC) ? 2 : 3; 2357 spin_lock_irqsave(&cp->lock, flags); 2358 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ 2359#ifdef USE_NAPI 2360 cas_mask_intr(cp); 2361 netif_rx_schedule(dev); 2362#else 2363 cas_rx_ringN(cp, ring, 0); 2364#endif 2365 status &= ~INTR_RX_DONE_ALT; 2366 } 2367 2368 if (status) 2369 cas_handle_irqN(dev, cp, status, ring); 2370 spin_unlock_irqrestore(&cp->lock, flags); 2371 return IRQ_HANDLED; 2372} 2373#endif 2374 2375#ifdef USE_PCI_INTB 2376/* everything but rx packets */ 2377static inline void cas_handle_irq1(struct cas *cp, const u32 status) 2378{ 2379 if (status & INTR_RX_BUF_UNAVAIL_1) { 2380 /* Frame arrived, no free RX buffers available. 2381 * NOTE: we can get this on a link transition. */ 2382 cas_post_rxds_ringN(cp, 1, 0); 2383 spin_lock(&cp->stat_lock[1]); 2384 cp->net_stats[1].rx_dropped++; 2385 spin_unlock(&cp->stat_lock[1]); 2386 } 2387 2388 if (status & INTR_RX_BUF_AE_1) 2389 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) - 2390 RX_AE_FREEN_VAL(1)); 2391 2392 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) 2393 cas_post_rxcs_ringN(cp, 1); 2394} 2395 2396/* ring 2 handles a few more events than 3 and 4 */ 2397static irqreturn_t cas_interrupt1(int irq, void *dev_id) 2398{ 2399 struct net_device *dev = dev_id; 2400 struct cas *cp = netdev_priv(dev); 2401 unsigned long flags; 2402 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); 2403 2404 /* check for shared interrupt */ 2405 if (status == 0) 2406 return IRQ_NONE; 2407 2408 spin_lock_irqsave(&cp->lock, flags); 2409 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ 2410#ifdef USE_NAPI 2411 cas_mask_intr(cp); 2412 netif_rx_schedule(dev); 2413#else 2414 cas_rx_ringN(cp, 1, 0); 2415#endif 2416 status &= ~INTR_RX_DONE_ALT; 2417 } 2418 if (status) 2419 cas_handle_irq1(cp, status); 2420 spin_unlock_irqrestore(&cp->lock, flags); 2421 return IRQ_HANDLED; 2422} 2423#endif 2424 2425static inline void cas_handle_irq(struct net_device *dev, 2426 struct cas *cp, const u32 status) 2427{ 2428 /* housekeeping interrupts */ 2429 if (status & INTR_ERROR_MASK) 2430 cas_abnormal_irq(dev, cp, status); 2431 2432 if (status & INTR_RX_BUF_UNAVAIL) { 2433 /* Frame arrived, no free RX buffers available. 2434 * NOTE: we can get this on a link transition. 2435 */ 2436 cas_post_rxds_ringN(cp, 0, 0); 2437 spin_lock(&cp->stat_lock[0]); 2438 cp->net_stats[0].rx_dropped++; 2439 spin_unlock(&cp->stat_lock[0]); 2440 } else if (status & INTR_RX_BUF_AE) { 2441 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) - 2442 RX_AE_FREEN_VAL(0)); 2443 } 2444 2445 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) 2446 cas_post_rxcs_ringN(dev, cp, 0); 2447} 2448 2449static irqreturn_t cas_interrupt(int irq, void *dev_id) 2450{ 2451 struct net_device *dev = dev_id; 2452 struct cas *cp = netdev_priv(dev); 2453 unsigned long flags; 2454 u32 status = readl(cp->regs + REG_INTR_STATUS); 2455 2456 if (status == 0) 2457 return IRQ_NONE; 2458 2459 spin_lock_irqsave(&cp->lock, flags); 2460 if (status & (INTR_TX_ALL | INTR_TX_INTME)) { 2461 cas_tx(dev, cp, status); 2462 status &= ~(INTR_TX_ALL | INTR_TX_INTME); 2463 } 2464 2465 if (status & INTR_RX_DONE) { 2466#ifdef USE_NAPI 2467 cas_mask_intr(cp); 2468 netif_rx_schedule(dev); 2469#else 2470 cas_rx_ringN(cp, 0, 0); 2471#endif 2472 status &= ~INTR_RX_DONE; 2473 } 2474 2475 if (status) 2476 cas_handle_irq(dev, cp, status); 2477 spin_unlock_irqrestore(&cp->lock, flags); 2478 return IRQ_HANDLED; 2479} 2480 2481 2482#ifdef USE_NAPI 2483static int cas_poll(struct net_device *dev, int *budget) 2484{ 2485 struct cas *cp = netdev_priv(dev); 2486 int i, enable_intr, todo, credits; 2487 u32 status = readl(cp->regs + REG_INTR_STATUS); 2488 unsigned long flags; 2489 2490 spin_lock_irqsave(&cp->lock, flags); 2491 cas_tx(dev, cp, status); 2492 spin_unlock_irqrestore(&cp->lock, flags); 2493 2494 /* NAPI rx packets. we spread the credits across all of the 2495 * rxc rings 2496 */ 2497 todo = min(*budget, dev->quota); 2498 2499 /* to make sure we're fair with the work we loop through each 2500 * ring N_RX_COMP_RING times with a request of 2501 * todo / N_RX_COMP_RINGS 2502 */ 2503 enable_intr = 1; 2504 credits = 0; 2505 for (i = 0; i < N_RX_COMP_RINGS; i++) { 2506 int j; 2507 for (j = 0; j < N_RX_COMP_RINGS; j++) { 2508 credits += cas_rx_ringN(cp, j, todo / N_RX_COMP_RINGS); 2509 if (credits >= todo) { 2510 enable_intr = 0; 2511 goto rx_comp; 2512 } 2513 } 2514 } 2515 2516rx_comp: 2517 *budget -= credits; 2518 dev->quota -= credits; 2519 2520 /* final rx completion */ 2521 spin_lock_irqsave(&cp->lock, flags); 2522 if (status) 2523 cas_handle_irq(dev, cp, status); 2524 2525#ifdef USE_PCI_INTB 2526 if (N_RX_COMP_RINGS > 1) { 2527 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); 2528 if (status) 2529 cas_handle_irq1(dev, cp, status); 2530 } 2531#endif 2532 2533#ifdef USE_PCI_INTC 2534 if (N_RX_COMP_RINGS > 2) { 2535 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2)); 2536 if (status) 2537 cas_handle_irqN(dev, cp, status, 2); 2538 } 2539#endif 2540 2541#ifdef USE_PCI_INTD 2542 if (N_RX_COMP_RINGS > 3) { 2543 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3)); 2544 if (status) 2545 cas_handle_irqN(dev, cp, status, 3); 2546 } 2547#endif 2548 spin_unlock_irqrestore(&cp->lock, flags); 2549 if (enable_intr) { 2550 netif_rx_complete(dev); 2551 cas_unmask_intr(cp); 2552 return 0; 2553 } 2554 return 1; 2555} 2556#endif 2557 2558#ifdef CONFIG_NET_POLL_CONTROLLER 2559static void cas_netpoll(struct net_device *dev) 2560{ 2561 struct cas *cp = netdev_priv(dev); 2562 2563 cas_disable_irq(cp, 0); 2564 cas_interrupt(cp->pdev->irq, dev); 2565 cas_enable_irq(cp, 0); 2566 2567#ifdef USE_PCI_INTB 2568 if (N_RX_COMP_RINGS > 1) { 2569 /* cas_interrupt1(); */ 2570 } 2571#endif 2572#ifdef USE_PCI_INTC 2573 if (N_RX_COMP_RINGS > 2) { 2574 /* cas_interruptN(); */ 2575 } 2576#endif 2577#ifdef USE_PCI_INTD 2578 if (N_RX_COMP_RINGS > 3) { 2579 /* cas_interruptN(); */ 2580 } 2581#endif 2582} 2583#endif 2584 2585static void cas_tx_timeout(struct net_device *dev) 2586{ 2587 struct cas *cp = netdev_priv(dev); 2588 2589 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name); 2590 if (!cp->hw_running) { 2591 printk("%s: hrm.. hw not running!\n", dev->name); 2592 return; 2593 } 2594 2595 printk(KERN_ERR "%s: MIF_STATE[%08x]\n", 2596 dev->name, readl(cp->regs + REG_MIF_STATE_MACHINE)); 2597 2598 printk(KERN_ERR "%s: MAC_STATE[%08x]\n", 2599 dev->name, readl(cp->regs + REG_MAC_STATE_MACHINE)); 2600 2601 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x] " 2602 "FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n", 2603 dev->name, 2604 readl(cp->regs + REG_TX_CFG), 2605 readl(cp->regs + REG_MAC_TX_STATUS), 2606 readl(cp->regs + REG_MAC_TX_CFG), 2607 readl(cp->regs + REG_TX_FIFO_PKT_CNT), 2608 readl(cp->regs + REG_TX_FIFO_WRITE_PTR), 2609 readl(cp->regs + REG_TX_FIFO_READ_PTR), 2610 readl(cp->regs + REG_TX_SM_1), 2611 readl(cp->regs + REG_TX_SM_2)); 2612 2613 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n", 2614 dev->name, 2615 readl(cp->regs + REG_RX_CFG), 2616 readl(cp->regs + REG_MAC_RX_STATUS), 2617 readl(cp->regs + REG_MAC_RX_CFG)); 2618 2619 printk(KERN_ERR "%s: HP_STATE[%08x:%08x:%08x:%08x]\n", 2620 dev->name, 2621 readl(cp->regs + REG_HP_STATE_MACHINE), 2622 readl(cp->regs + REG_HP_STATUS0), 2623 readl(cp->regs + REG_HP_STATUS1), 2624 readl(cp->regs + REG_HP_STATUS2)); 2625 2626 atomic_inc(&cp->reset_task_pending); 2627 atomic_inc(&cp->reset_task_pending_all); 2628 schedule_work(&cp->reset_task); 2629} 2630 2631static inline int cas_intme(int ring, int entry) 2632{ 2633 /* Algorithm: IRQ every 1/2 of descriptors. */ 2634 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1))) 2635 return 1; 2636 return 0; 2637} 2638 2639 2640static void cas_write_txd(struct cas *cp, int ring, int entry, 2641 dma_addr_t mapping, int len, u64 ctrl, int last) 2642{ 2643 struct cas_tx_desc *txd = cp->init_txds[ring] + entry; 2644 2645 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len); 2646 if (cas_intme(ring, entry)) 2647 ctrl |= TX_DESC_INTME; 2648 if (last) 2649 ctrl |= TX_DESC_EOF; 2650 txd->control = cpu_to_le64(ctrl); 2651 txd->buffer = cpu_to_le64(mapping); 2652} 2653 2654static inline void *tx_tiny_buf(struct cas *cp, const int ring, 2655 const int entry) 2656{ 2657 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry; 2658} 2659 2660static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring, 2661 const int entry, const int tentry) 2662{ 2663 cp->tx_tiny_use[ring][tentry].nbufs++; 2664 cp->tx_tiny_use[ring][entry].used = 1; 2665 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry; 2666} 2667 2668static inline int cas_xmit_tx_ringN(struct cas *cp, int ring, 2669 struct sk_buff *skb) 2670{ 2671 struct net_device *dev = cp->dev; 2672 int entry, nr_frags, frag, tabort, tentry; 2673 dma_addr_t mapping; 2674 unsigned long flags; 2675 u64 ctrl; 2676 u32 len; 2677 2678 spin_lock_irqsave(&cp->tx_lock[ring], flags); 2679 2680 /* This is a hard error, log it. */ 2681 if (TX_BUFFS_AVAIL(cp, ring) <= 2682 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) { 2683 netif_stop_queue(dev); 2684 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); 2685 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when " 2686 "queue awake!\n", dev->name); 2687 return 1; 2688 } 2689 2690 ctrl = 0; 2691 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2692 const u64 csum_start_off = skb_transport_offset(skb); 2693 const u64 csum_stuff_off = csum_start_off + skb->csum_offset; 2694 2695 ctrl = TX_DESC_CSUM_EN | 2696 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) | 2697 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off); 2698 } 2699 2700 entry = cp->tx_new[ring]; 2701 cp->tx_skbs[ring][entry] = skb; 2702 2703 nr_frags = skb_shinfo(skb)->nr_frags; 2704 len = skb_headlen(skb); 2705 mapping = pci_map_page(cp->pdev, virt_to_page(skb->data), 2706 offset_in_page(skb->data), len, 2707 PCI_DMA_TODEVICE); 2708 2709 tentry = entry; 2710 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len); 2711 if (unlikely(tabort)) { 2712 /* NOTE: len is always > tabort */ 2713 cas_write_txd(cp, ring, entry, mapping, len - tabort, 2714 ctrl | TX_DESC_SOF, 0); 2715 entry = TX_DESC_NEXT(ring, entry); 2716 2717 skb_copy_from_linear_data_offset(skb, len - tabort, 2718 tx_tiny_buf(cp, ring, entry), tabort); 2719 mapping = tx_tiny_map(cp, ring, entry, tentry); 2720 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl, 2721 (nr_frags == 0)); 2722 } else { 2723 cas_write_txd(cp, ring, entry, mapping, len, ctrl | 2724 TX_DESC_SOF, (nr_frags == 0)); 2725 } 2726 entry = TX_DESC_NEXT(ring, entry); 2727 2728 for (frag = 0; frag < nr_frags; frag++) { 2729 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 2730 2731 len = fragp->size; 2732 mapping = pci_map_page(cp->pdev, fragp->page, 2733 fragp->page_offset, len, 2734 PCI_DMA_TODEVICE); 2735 2736 tabort = cas_calc_tabort(cp, fragp->page_offset, len); 2737 if (unlikely(tabort)) { 2738 void *addr; 2739 2740 /* NOTE: len is always > tabort */ 2741 cas_write_txd(cp, ring, entry, mapping, len - tabort, 2742 ctrl, 0); 2743 entry = TX_DESC_NEXT(ring, entry); 2744 2745 addr = cas_page_map(fragp->page); 2746 memcpy(tx_tiny_buf(cp, ring, entry), 2747 addr + fragp->page_offset + len - tabort, 2748 tabort); 2749 cas_page_unmap(addr); 2750 mapping = tx_tiny_map(cp, ring, entry, tentry); 2751 len = tabort; 2752 } 2753 2754 cas_write_txd(cp, ring, entry, mapping, len, ctrl, 2755 (frag + 1 == nr_frags)); 2756 entry = TX_DESC_NEXT(ring, entry); 2757 } 2758 2759 cp->tx_new[ring] = entry; 2760 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)) 2761 netif_stop_queue(dev); 2762 2763 if (netif_msg_tx_queued(cp)) 2764 printk(KERN_DEBUG "%s: tx[%d] queued, slot %d, skblen %d, " 2765 "avail %d\n", 2766 dev->name, ring, entry, skb->len, 2767 TX_BUFFS_AVAIL(cp, ring)); 2768 writel(entry, cp->regs + REG_TX_KICKN(ring)); 2769 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); 2770 return 0; 2771} 2772 2773static int cas_start_xmit(struct sk_buff *skb, struct net_device *dev) 2774{ 2775 struct cas *cp = netdev_priv(dev); 2776 2777 /* this is only used as a load-balancing hint, so it doesn't 2778 * need to be SMP safe 2779 */ 2780 static int ring; 2781 2782 if (skb_padto(skb, cp->min_frame_size)) 2783 return 0; 2784 2785 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb)) 2786 return 1; 2787 dev->trans_start = jiffies; 2788 return 0; 2789} 2790 2791static void cas_init_tx_dma(struct cas *cp) 2792{ 2793 u64 desc_dma = cp->block_dvma; 2794 unsigned long off; 2795 u32 val; 2796 int i; 2797 2798 /* set up tx completion writeback registers. must be 8-byte aligned */ 2799#ifdef USE_TX_COMPWB 2800 off = offsetof(struct cas_init_block, tx_compwb); 2801 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI); 2802 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW); 2803#endif 2804 2805 /* enable completion writebacks, enable paced mode, 2806 * disable read pipe, and disable pre-interrupt compwbs 2807 */ 2808 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 | 2809 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 | 2810 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE | 2811 TX_CFG_INTR_COMPWB_DIS; 2812 2813 /* write out tx ring info and tx desc bases */ 2814 for (i = 0; i < MAX_TX_RINGS; i++) { 2815 off = (unsigned long) cp->init_txds[i] - 2816 (unsigned long) cp->init_block; 2817 2818 val |= CAS_TX_RINGN_BASE(i); 2819 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i)); 2820 writel((desc_dma + off) & 0xffffffff, cp->regs + 2821 REG_TX_DBN_LOW(i)); 2822 /* don't zero out the kick register here as the system 2823 * will wedge 2824 */ 2825 } 2826 writel(val, cp->regs + REG_TX_CFG); 2827 2828 /* program max burst sizes. these numbers should be different 2829 * if doing QoS. 2830 */ 2831#ifdef USE_QOS 2832 writel(0x800, cp->regs + REG_TX_MAXBURST_0); 2833 writel(0x1600, cp->regs + REG_TX_MAXBURST_1); 2834 writel(0x2400, cp->regs + REG_TX_MAXBURST_2); 2835 writel(0x4800, cp->regs + REG_TX_MAXBURST_3); 2836#else 2837 writel(0x800, cp->regs + REG_TX_MAXBURST_0); 2838 writel(0x800, cp->regs + REG_TX_MAXBURST_1); 2839 writel(0x800, cp->regs + REG_TX_MAXBURST_2); 2840 writel(0x800, cp->regs + REG_TX_MAXBURST_3); 2841#endif 2842} 2843 2844/* Must be invoked under cp->lock. */ 2845static inline void cas_init_dma(struct cas *cp) 2846{ 2847 cas_init_tx_dma(cp); 2848 cas_init_rx_dma(cp); 2849} 2850 2851/* Must be invoked under cp->lock. */ 2852static u32 cas_setup_multicast(struct cas *cp) 2853{ 2854 u32 rxcfg = 0; 2855 int i; 2856 2857 if (cp->dev->flags & IFF_PROMISC) { 2858 rxcfg |= MAC_RX_CFG_PROMISC_EN; 2859 2860 } else if (cp->dev->flags & IFF_ALLMULTI) { 2861 for (i=0; i < 16; i++) 2862 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i)); 2863 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; 2864 2865 } else { 2866 u16 hash_table[16]; 2867 u32 crc; 2868 struct dev_mc_list *dmi = cp->dev->mc_list; 2869 int i; 2870 2871 /* use the alternate mac address registers for the 2872 * first 15 multicast addresses 2873 */ 2874 for (i = 1; i <= CAS_MC_EXACT_MATCH_SIZE; i++) { 2875 if (!dmi) { 2876 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 0)); 2877 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 1)); 2878 writel(0x0, cp->regs + REG_MAC_ADDRN(i*3 + 2)); 2879 continue; 2880 } 2881 writel((dmi->dmi_addr[4] << 8) | dmi->dmi_addr[5], 2882 cp->regs + REG_MAC_ADDRN(i*3 + 0)); 2883 writel((dmi->dmi_addr[2] << 8) | dmi->dmi_addr[3], 2884 cp->regs + REG_MAC_ADDRN(i*3 + 1)); 2885 writel((dmi->dmi_addr[0] << 8) | dmi->dmi_addr[1], 2886 cp->regs + REG_MAC_ADDRN(i*3 + 2)); 2887 dmi = dmi->next; 2888 } 2889 2890 /* use hw hash table for the next series of 2891 * multicast addresses 2892 */ 2893 memset(hash_table, 0, sizeof(hash_table)); 2894 while (dmi) { 2895 crc = ether_crc_le(ETH_ALEN, dmi->dmi_addr); 2896 crc >>= 24; 2897 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); 2898 dmi = dmi->next; 2899 } 2900 for (i=0; i < 16; i++) 2901 writel(hash_table[i], cp->regs + 2902 REG_MAC_HASH_TABLEN(i)); 2903 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; 2904 } 2905 2906 return rxcfg; 2907} 2908 2909/* must be invoked under cp->stat_lock[N_TX_RINGS] */ 2910static void cas_clear_mac_err(struct cas *cp) 2911{ 2912 writel(0, cp->regs + REG_MAC_COLL_NORMAL); 2913 writel(0, cp->regs + REG_MAC_COLL_FIRST); 2914 writel(0, cp->regs + REG_MAC_COLL_EXCESS); 2915 writel(0, cp->regs + REG_MAC_COLL_LATE); 2916 writel(0, cp->regs + REG_MAC_TIMER_DEFER); 2917 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK); 2918 writel(0, cp->regs + REG_MAC_RECV_FRAME); 2919 writel(0, cp->regs + REG_MAC_LEN_ERR); 2920 writel(0, cp->regs + REG_MAC_ALIGN_ERR); 2921 writel(0, cp->regs + REG_MAC_FCS_ERR); 2922 writel(0, cp->regs + REG_MAC_RX_CODE_ERR); 2923} 2924 2925 2926static void cas_mac_reset(struct cas *cp) 2927{ 2928 int i; 2929 2930 /* do both TX and RX reset */ 2931 writel(0x1, cp->regs + REG_MAC_TX_RESET); 2932 writel(0x1, cp->regs + REG_MAC_RX_RESET); 2933 2934 /* wait for TX */ 2935 i = STOP_TRIES; 2936 while (i-- > 0) { 2937 if (readl(cp->regs + REG_MAC_TX_RESET) == 0) 2938 break; 2939 udelay(10); 2940 } 2941 2942 /* wait for RX */ 2943 i = STOP_TRIES; 2944 while (i-- > 0) { 2945 if (readl(cp->regs + REG_MAC_RX_RESET) == 0) 2946 break; 2947 udelay(10); 2948 } 2949 2950 if (readl(cp->regs + REG_MAC_TX_RESET) | 2951 readl(cp->regs + REG_MAC_RX_RESET)) 2952 printk(KERN_ERR "%s: mac tx[%d]/rx[%d] reset failed [%08x]\n", 2953 cp->dev->name, readl(cp->regs + REG_MAC_TX_RESET), 2954 readl(cp->regs + REG_MAC_RX_RESET), 2955 readl(cp->regs + REG_MAC_STATE_MACHINE)); 2956} 2957 2958 2959/* Must be invoked under cp->lock. */ 2960static void cas_init_mac(struct cas *cp) 2961{ 2962 unsigned char *e = &cp->dev->dev_addr[0]; 2963 int i; 2964#ifdef CONFIG_CASSINI_MULTICAST_REG_WRITE 2965 u32 rxcfg; 2966#endif 2967 cas_mac_reset(cp); 2968 2969 /* setup core arbitration weight register */ 2970 writel(CAWR_RR_DIS, cp->regs + REG_CAWR); 2971 2972#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA) 2973 /* set the infinite burst register for chips that don't have 2974 * pci issues. 2975 */ 2976 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0) 2977 writel(INF_BURST_EN, cp->regs + REG_INF_BURST); 2978#endif 2979 2980 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE); 2981 2982 writel(0x00, cp->regs + REG_MAC_IPG0); 2983 writel(0x08, cp->regs + REG_MAC_IPG1); 2984 writel(0x04, cp->regs + REG_MAC_IPG2); 2985 2986 /* change later for 802.3z */ 2987 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 2988 2989 /* min frame + FCS */ 2990 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN); 2991 2992 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we 2993 * specify the maximum frame size to prevent RX tag errors on 2994 * oversized frames. 2995 */ 2996 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) | 2997 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME, 2998 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)), 2999 cp->regs + REG_MAC_FRAMESIZE_MAX); 3000 3001 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size) 3002 writel(0x41, cp->regs + REG_MAC_PA_SIZE); 3003 else 3004 writel(0x07, cp->regs + REG_MAC_PA_SIZE); 3005 writel(0x04, cp->regs + REG_MAC_JAM_SIZE); 3006 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT); 3007 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE); 3008 3009 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED); 3010 3011 writel(0, cp->regs + REG_MAC_ADDR_FILTER0); 3012 writel(0, cp->regs + REG_MAC_ADDR_FILTER1); 3013 writel(0, cp->regs + REG_MAC_ADDR_FILTER2); 3014 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK); 3015 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK); 3016 3017 /* setup mac address in perfect filter array */ 3018 for (i = 0; i < 45; i++) 3019 writel(0x0, cp->regs + REG_MAC_ADDRN(i)); 3020 3021 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0)); 3022 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1)); 3023 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2)); 3024 3025 writel(0x0001, cp->regs + REG_MAC_ADDRN(42)); 3026 writel(0xc200, cp->regs + REG_MAC_ADDRN(43)); 3027 writel(0x0180, cp->regs + REG_MAC_ADDRN(44)); 3028 3029#ifndef CONFIG_CASSINI_MULTICAST_REG_WRITE 3030 cp->mac_rx_cfg = cas_setup_multicast(cp); 3031#else 3032 /* WTZ: Do what Adrian did in cas_set_multicast. Doing 3033 * a writel does not seem to be necessary because Cassini 3034 * seems to preserve the configuration when we do the reset. 3035 * If the chip is in trouble, though, it is not clear if we 3036 * can really count on this behavior. cas_set_multicast uses 3037 * spin_lock_irqsave, but we are called only in cas_init_hw and 3038 * cas_init_hw is protected by cas_lock_all, which calls 3039 * spin_lock_irq (so it doesn't need to save the flags, and 3040 * we should be OK for the writel, as that is the only 3041 * difference). 3042 */ 3043 cp->mac_rx_cfg = rxcfg = cas_setup_multicast(cp); 3044 writel(rxcfg, cp->regs + REG_MAC_RX_CFG); 3045#endif 3046 spin_lock(&cp->stat_lock[N_TX_RINGS]); 3047 cas_clear_mac_err(cp); 3048 spin_unlock(&cp->stat_lock[N_TX_RINGS]); 3049 3050 /* Setup MAC interrupts. We want to get all of the interesting 3051 * counter expiration events, but we do not want to hear about 3052 * normal rx/tx as the DMA engine tells us that. 3053 */ 3054 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK); 3055 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); 3056 3057 /* Don't enable even the PAUSE interrupts for now, we 3058 * make no use of those events other than to record them. 3059 */ 3060 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK); 3061} 3062 3063/* Must be invoked under cp->lock. */ 3064static void cas_init_pause_thresholds(struct cas *cp) 3065{ 3066 /* Calculate pause thresholds. Setting the OFF threshold to the 3067 * full RX fifo size effectively disables PAUSE generation 3068 */ 3069 if (cp->rx_fifo_size <= (2 * 1024)) { 3070 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size; 3071 } else { 3072 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63; 3073 if (max_frame * 3 > cp->rx_fifo_size) { 3074 cp->rx_pause_off = 7104; 3075 cp->rx_pause_on = 960; 3076 } else { 3077 int off = (cp->rx_fifo_size - (max_frame * 2)); 3078 int on = off - max_frame; 3079 cp->rx_pause_off = off; 3080 cp->rx_pause_on = on; 3081 } 3082 } 3083} 3084 3085static int cas_vpd_match(const void __iomem *p, const char *str) 3086{ 3087 int len = strlen(str) + 1; 3088 int i; 3089 3090 for (i = 0; i < len; i++) { 3091 if (readb(p + i) != str[i]) 3092 return 0; 3093 } 3094 return 1; 3095} 3096 3097 3098/* get the mac address by reading the vpd information in the rom. 3099 * also get the phy type and determine if there's an entropy generator. 3100 * NOTE: this is a bit convoluted for the following reasons: 3101 * 1) vpd info has order-dependent mac addresses for multinic cards 3102 * 2) the only way to determine the nic order is to use the slot 3103 * number. 3104 * 3) fiber cards don't have bridges, so their slot numbers don't 3105 * mean anything. 3106 * 4) we don't actually know we have a fiber card until after 3107 * the mac addresses are parsed. 3108 */ 3109static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr, 3110 const int offset) 3111{ 3112 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START; 3113 void __iomem *base, *kstart; 3114 int i, len; 3115 int found = 0; 3116#define VPD_FOUND_MAC 0x01 3117#define VPD_FOUND_PHY 0x02 3118 3119 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */ 3120 int mac_off = 0; 3121 3122 /* give us access to the PROM */ 3123 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD, 3124 cp->regs + REG_BIM_LOCAL_DEV_EN); 3125 3126 /* check for an expansion rom */ 3127 if (readb(p) != 0x55 || readb(p + 1) != 0xaa) 3128 goto use_random_mac_addr; 3129 3130 /* search for beginning of vpd */ 3131 base = NULL; 3132 for (i = 2; i < EXPANSION_ROM_SIZE; i++) { 3133 /* check for PCIR */ 3134 if ((readb(p + i + 0) == 0x50) && 3135 (readb(p + i + 1) == 0x43) && 3136 (readb(p + i + 2) == 0x49) && 3137 (readb(p + i + 3) == 0x52)) { 3138 base = p + (readb(p + i + 8) | 3139 (readb(p + i + 9) << 8)); 3140 break; 3141 } 3142 } 3143 3144 if (!base || (readb(base) != 0x82)) 3145 goto use_random_mac_addr; 3146 3147 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3; 3148 while (i < EXPANSION_ROM_SIZE) { 3149 if (readb(base + i) != 0x90) /* no vpd found */ 3150 goto use_random_mac_addr; 3151 3152 /* found a vpd field */ 3153 len = readb(base + i + 1) | (readb(base + i + 2) << 8); 3154 3155 /* extract keywords */ 3156 kstart = base + i + 3; 3157 p = kstart; 3158 while ((p - kstart) < len) { 3159 int klen = readb(p + 2); 3160 int j; 3161 char type; 3162 3163 p += 3; 3164 3165 /* look for the following things: 3166 * -- correct length == 29 3167 * 3 (type) + 2 (size) + 3168 * 18 (strlen("local-mac-address") + 1) + 3169 * 6 (mac addr) 3170 * -- VPD Instance 'I' 3171 * -- VPD Type Bytes 'B' 3172 * -- VPD data length == 6 3173 * -- property string == local-mac-address 3174 * 3175 * -- correct length == 24 3176 * 3 (type) + 2 (size) + 3177 * 12 (strlen("entropy-dev") + 1) + 3178 * 7 (strlen("vms110") + 1) 3179 * -- VPD Instance 'I' 3180 * -- VPD Type String 'B' 3181 * -- VPD data length == 7 3182 * -- property string == entropy-dev 3183 * 3184 * -- correct length == 18 3185 * 3 (type) + 2 (size) + 3186 * 9 (strlen("phy-type") + 1) + 3187 * 4 (strlen("pcs") + 1) 3188 * -- VPD Instance 'I' 3189 * -- VPD Type String 'S' 3190 * -- VPD data length == 4 3191 * -- property string == phy-type 3192 * 3193 * -- correct length == 23 3194 * 3 (type) + 2 (size) + 3195 * 14 (strlen("phy-interface") + 1) + 3196 * 4 (strlen("pcs") + 1) 3197 * -- VPD Instance 'I' 3198 * -- VPD Type String 'S' 3199 * -- VPD data length == 4 3200 * -- property string == phy-interface 3201 */ 3202 if (readb(p) != 'I') 3203 goto next; 3204 3205 /* finally, check string and length */ 3206 type = readb(p + 3); 3207 if (type == 'B') { 3208 if ((klen == 29) && readb(p + 4) == 6 && 3209 cas_vpd_match(p + 5, 3210 "local-mac-address")) { 3211 if (mac_off++ > offset) 3212 goto next; 3213 3214 /* set mac address */ 3215 for (j = 0; j < 6; j++) 3216 dev_addr[j] = 3217 readb(p + 23 + j); 3218 goto found_mac; 3219 } 3220 } 3221 3222 if (type != 'S') 3223 goto next; 3224 3225#ifdef USE_ENTROPY_DEV 3226 if ((klen == 24) && 3227 cas_vpd_match(p + 5, "entropy-dev") && 3228 cas_vpd_match(p + 17, "vms110")) { 3229 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV; 3230 goto next; 3231 } 3232#endif 3233 3234 if (found & VPD_FOUND_PHY) 3235 goto next; 3236 3237 if ((klen == 18) && readb(p + 4) == 4 && 3238 cas_vpd_match(p + 5, "phy-type")) { 3239 if (cas_vpd_match(p + 14, "pcs")) { 3240 phy_type = CAS_PHY_SERDES; 3241 goto found_phy; 3242 } 3243 } 3244 3245 if ((klen == 23) && readb(p + 4) == 4 && 3246 cas_vpd_match(p + 5, "phy-interface")) { 3247 if (cas_vpd_match(p + 19, "pcs")) { 3248 phy_type = CAS_PHY_SERDES; 3249 goto found_phy; 3250 } 3251 } 3252found_mac: 3253 found |= VPD_FOUND_MAC; 3254 goto next; 3255 3256found_phy: 3257 found |= VPD_FOUND_PHY; 3258 3259next: 3260 p += klen; 3261 } 3262 i += len + 3; 3263 } 3264 3265use_random_mac_addr: 3266 if (found & VPD_FOUND_MAC) 3267 goto done; 3268 3269 /* Sun MAC prefix then 3 random bytes. */ 3270 printk(PFX "MAC address not found in ROM VPD\n"); 3271 dev_addr[0] = 0x08; 3272 dev_addr[1] = 0x00; 3273 dev_addr[2] = 0x20; 3274 get_random_bytes(dev_addr + 3, 3); 3275 3276done: 3277 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN); 3278 return phy_type; 3279} 3280 3281/* check pci invariants */ 3282static void cas_check_pci_invariants(struct cas *cp) 3283{ 3284 struct pci_dev *pdev = cp->pdev; 3285 u8 rev; 3286 3287 cp->cas_flags = 0; 3288 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev); 3289 if ((pdev->vendor == PCI_VENDOR_ID_SUN) && 3290 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) { 3291 if (rev >= CAS_ID_REVPLUS) 3292 cp->cas_flags |= CAS_FLAG_REG_PLUS; 3293 if (rev < CAS_ID_REVPLUS02u) 3294 cp->cas_flags |= CAS_FLAG_TARGET_ABORT; 3295 3296 /* Original Cassini supports HW CSUM, but it's not 3297 * enabled by default as it can trigger TX hangs. 3298 */ 3299 if (rev < CAS_ID_REV2) 3300 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM; 3301 } else { 3302 /* Only sun has original cassini chips. */ 3303 cp->cas_flags |= CAS_FLAG_REG_PLUS; 3304 3305 /* We use a flag because the same phy might be externally 3306 * connected. 3307 */ 3308 if ((pdev->vendor == PCI_VENDOR_ID_NS) && 3309 (pdev->device == PCI_DEVICE_ID_NS_SATURN)) 3310 cp->cas_flags |= CAS_FLAG_SATURN; 3311 } 3312} 3313 3314 3315static int cas_check_invariants(struct cas *cp) 3316{ 3317 struct pci_dev *pdev = cp->pdev; 3318 u32 cfg; 3319 int i; 3320 3321 /* get page size for rx buffers. */ 3322 cp->page_order = 0; 3323#ifdef USE_PAGE_ORDER 3324 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) { 3325 /* see if we can allocate larger pages */ 3326 struct page *page = alloc_pages(GFP_ATOMIC, 3327 CAS_JUMBO_PAGE_SHIFT - 3328 PAGE_SHIFT); 3329 if (page) { 3330 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT); 3331 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT; 3332 } else { 3333 printk(PFX "MTU limited to %d bytes\n", CAS_MAX_MTU); 3334 } 3335 } 3336#endif 3337 cp->page_size = (PAGE_SIZE << cp->page_order); 3338 3339 /* Fetch the FIFO configurations. */ 3340 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64; 3341 cp->rx_fifo_size = RX_FIFO_SIZE; 3342 3343 /* finish phy determination. MDIO1 takes precedence over MDIO0 if 3344 * they're both connected. 3345 */ 3346 cp->phy_type = cas_get_vpd_info(cp, cp->dev->dev_addr, 3347 PCI_SLOT(pdev->devfn)); 3348 if (cp->phy_type & CAS_PHY_SERDES) { 3349 cp->cas_flags |= CAS_FLAG_1000MB_CAP; 3350 return 0; /* no more checking needed */ 3351 } 3352 3353 /* MII */ 3354 cfg = readl(cp->regs + REG_MIF_CFG); 3355 if (cfg & MIF_CFG_MDIO_1) { 3356 cp->phy_type = CAS_PHY_MII_MDIO1; 3357 } else if (cfg & MIF_CFG_MDIO_0) { 3358 cp->phy_type = CAS_PHY_MII_MDIO0; 3359 } 3360 3361 cas_mif_poll(cp, 0); 3362 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); 3363 3364 for (i = 0; i < 32; i++) { 3365 u32 phy_id; 3366 int j; 3367 3368 for (j = 0; j < 3; j++) { 3369 cp->phy_addr = i; 3370 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16; 3371 phy_id |= cas_phy_read(cp, MII_PHYSID2); 3372 if (phy_id && (phy_id != 0xFFFFFFFF)) { 3373 cp->phy_id = phy_id; 3374 goto done; 3375 } 3376 } 3377 } 3378 printk(KERN_ERR PFX "MII phy did not respond [%08x]\n", 3379 readl(cp->regs + REG_MIF_STATE_MACHINE)); 3380 return -1; 3381 3382done: 3383 /* see if we can do gigabit */ 3384 cfg = cas_phy_read(cp, MII_BMSR); 3385 if ((cfg & CAS_BMSR_1000_EXTEND) && 3386 cas_phy_read(cp, CAS_MII_1000_EXTEND)) 3387 cp->cas_flags |= CAS_FLAG_1000MB_CAP; 3388 return 0; 3389} 3390 3391/* Must be invoked under cp->lock. */ 3392static inline void cas_start_dma(struct cas *cp) 3393{ 3394 int i; 3395 u32 val; 3396 int txfailed = 0; 3397 3398 /* enable dma */ 3399 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN; 3400 writel(val, cp->regs + REG_TX_CFG); 3401 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN; 3402 writel(val, cp->regs + REG_RX_CFG); 3403 3404 /* enable the mac */ 3405 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN; 3406 writel(val, cp->regs + REG_MAC_TX_CFG); 3407 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN; 3408 writel(val, cp->regs + REG_MAC_RX_CFG); 3409 3410 i = STOP_TRIES; 3411 while (i-- > 0) { 3412 val = readl(cp->regs + REG_MAC_TX_CFG); 3413 if ((val & MAC_TX_CFG_EN)) 3414 break; 3415 udelay(10); 3416 } 3417 if (i < 0) txfailed = 1; 3418 i = STOP_TRIES; 3419 while (i-- > 0) { 3420 val = readl(cp->regs + REG_MAC_RX_CFG); 3421 if ((val & MAC_RX_CFG_EN)) { 3422 if (txfailed) { 3423 printk(KERN_ERR 3424 "%s: enabling mac failed [tx:%08x:%08x].\n", 3425 cp->dev->name, 3426 readl(cp->regs + REG_MIF_STATE_MACHINE), 3427 readl(cp->regs + REG_MAC_STATE_MACHINE)); 3428 } 3429 goto enable_rx_done; 3430 } 3431 udelay(10); 3432 } 3433 printk(KERN_ERR "%s: enabling mac failed [%s:%08x:%08x].\n", 3434 cp->dev->name, 3435 (txfailed? "tx,rx":"rx"), 3436 readl(cp->regs + REG_MIF_STATE_MACHINE), 3437 readl(cp->regs + REG_MAC_STATE_MACHINE)); 3438 3439enable_rx_done: 3440 cas_unmask_intr(cp); /* enable interrupts */ 3441 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); 3442 writel(0, cp->regs + REG_RX_COMP_TAIL); 3443 3444 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 3445 if (N_RX_DESC_RINGS > 1) 3446 writel(RX_DESC_RINGN_SIZE(1) - 4, 3447 cp->regs + REG_PLUS_RX_KICK1); 3448 3449 for (i = 1; i < N_RX_COMP_RINGS; i++) 3450 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i)); 3451 } 3452} 3453 3454/* Must be invoked under cp->lock. */ 3455static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd, 3456 int *pause) 3457{ 3458 u32 val = readl(cp->regs + REG_PCS_MII_LPA); 3459 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0; 3460 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00; 3461 if (val & PCS_MII_LPA_ASYM_PAUSE) 3462 *pause |= 0x10; 3463 *spd = 1000; 3464} 3465 3466/* Must be invoked under cp->lock. */ 3467static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd, 3468 int *pause) 3469{ 3470 u32 val; 3471 3472 *fd = 0; 3473 *spd = 10; 3474 *pause = 0; 3475 3476 /* use GMII registers */ 3477 val = cas_phy_read(cp, MII_LPA); 3478 if (val & CAS_LPA_PAUSE) 3479 *pause = 0x01; 3480 3481 if (val & CAS_LPA_ASYM_PAUSE) 3482 *pause |= 0x10; 3483 3484 if (val & LPA_DUPLEX) 3485 *fd = 1; 3486 if (val & LPA_100) 3487 *spd = 100; 3488 3489 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 3490 val = cas_phy_read(cp, CAS_MII_1000_STATUS); 3491 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF)) 3492 *spd = 1000; 3493 if (val & CAS_LPA_1000FULL) 3494 *fd = 1; 3495 } 3496} 3497 3498/* A link-up condition has occurred, initialize and enable the 3499 * rest of the chip. 3500 * 3501 * Must be invoked under cp->lock. 3502 */ 3503static void cas_set_link_modes(struct cas *cp) 3504{ 3505 u32 val; 3506 int full_duplex, speed, pause; 3507 3508 full_duplex = 0; 3509 speed = 10; 3510 pause = 0; 3511 3512 if (CAS_PHY_MII(cp->phy_type)) { 3513 cas_mif_poll(cp, 0); 3514 val = cas_phy_read(cp, MII_BMCR); 3515 if (val & BMCR_ANENABLE) { 3516 cas_read_mii_link_mode(cp, &full_duplex, &speed, 3517 &pause); 3518 } else { 3519 if (val & BMCR_FULLDPLX) 3520 full_duplex = 1; 3521 3522 if (val & BMCR_SPEED100) 3523 speed = 100; 3524 else if (val & CAS_BMCR_SPEED1000) 3525 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 3526 1000 : 100; 3527 } 3528 cas_mif_poll(cp, 1); 3529 3530 } else { 3531 val = readl(cp->regs + REG_PCS_MII_CTRL); 3532 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause); 3533 if ((val & PCS_MII_AUTONEG_EN) == 0) { 3534 if (val & PCS_MII_CTRL_DUPLEX) 3535 full_duplex = 1; 3536 } 3537 } 3538 3539 if (netif_msg_link(cp)) 3540 printk(KERN_INFO "%s: Link up at %d Mbps, %s-duplex.\n", 3541 cp->dev->name, speed, (full_duplex ? "full" : "half")); 3542 3543 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED; 3544 if (CAS_PHY_MII(cp->phy_type)) { 3545 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN; 3546 if (!full_duplex) 3547 val |= MAC_XIF_DISABLE_ECHO; 3548 } 3549 if (full_duplex) 3550 val |= MAC_XIF_FDPLX_LED; 3551 if (speed == 1000) 3552 val |= MAC_XIF_GMII_MODE; 3553 writel(val, cp->regs + REG_MAC_XIF_CFG); 3554 3555 /* deal with carrier and collision detect. */ 3556 val = MAC_TX_CFG_IPG_EN; 3557 if (full_duplex) { 3558 val |= MAC_TX_CFG_IGNORE_CARRIER; 3559 val |= MAC_TX_CFG_IGNORE_COLL; 3560 } else { 3561#ifndef USE_CSMA_CD_PROTO 3562 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN; 3563 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM; 3564#endif 3565 } 3566 /* val now set up for REG_MAC_TX_CFG */ 3567 3568 if ((speed == 1000) && !full_duplex) { 3569 writel(val | MAC_TX_CFG_CARRIER_EXTEND, 3570 cp->regs + REG_MAC_TX_CFG); 3571 3572 val = readl(cp->regs + REG_MAC_RX_CFG); 3573 val &= ~MAC_RX_CFG_STRIP_FCS; 3574 writel(val | MAC_RX_CFG_CARRIER_EXTEND, 3575 cp->regs + REG_MAC_RX_CFG); 3576 3577 writel(0x200, cp->regs + REG_MAC_SLOT_TIME); 3578 3579 cp->crc_size = 4; 3580 /* minimum size gigabit frame at half duplex */ 3581 cp->min_frame_size = CAS_1000MB_MIN_FRAME; 3582 3583 } else { 3584 writel(val, cp->regs + REG_MAC_TX_CFG); 3585 3586 val = readl(cp->regs + REG_MAC_RX_CFG); 3587 if (full_duplex) { 3588 val |= MAC_RX_CFG_STRIP_FCS; 3589 cp->crc_size = 0; 3590 cp->min_frame_size = CAS_MIN_MTU; 3591 } else { 3592 val &= ~MAC_RX_CFG_STRIP_FCS; 3593 cp->crc_size = 4; 3594 cp->min_frame_size = CAS_MIN_FRAME; 3595 } 3596 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND, 3597 cp->regs + REG_MAC_RX_CFG); 3598 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 3599 } 3600 3601 if (netif_msg_link(cp)) { 3602 if (pause & 0x01) { 3603 printk(KERN_INFO "%s: Pause is enabled " 3604 "(rxfifo: %d off: %d on: %d)\n", 3605 cp->dev->name, 3606 cp->rx_fifo_size, 3607 cp->rx_pause_off, 3608 cp->rx_pause_on); 3609 } else if (pause & 0x10) { 3610 printk(KERN_INFO "%s: TX pause enabled\n", 3611 cp->dev->name); 3612 } else { 3613 printk(KERN_INFO "%s: Pause is disabled\n", 3614 cp->dev->name); 3615 } 3616 } 3617 3618 val = readl(cp->regs + REG_MAC_CTRL_CFG); 3619 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN); 3620 if (pause) { /* symmetric or asymmetric pause */ 3621 val |= MAC_CTRL_CFG_SEND_PAUSE_EN; 3622 if (pause & 0x01) { /* symmetric pause */ 3623 val |= MAC_CTRL_CFG_RECV_PAUSE_EN; 3624 } 3625 } 3626 writel(val, cp->regs + REG_MAC_CTRL_CFG); 3627 cas_start_dma(cp); 3628} 3629 3630/* Must be invoked under cp->lock. */ 3631static void cas_init_hw(struct cas *cp, int restart_link) 3632{ 3633 if (restart_link) 3634 cas_phy_init(cp); 3635 3636 cas_init_pause_thresholds(cp); 3637 cas_init_mac(cp); 3638 cas_init_dma(cp); 3639 3640 if (restart_link) { 3641 /* Default aneg parameters */ 3642 cp->timer_ticks = 0; 3643 cas_begin_auto_negotiation(cp, NULL); 3644 } else if (cp->lstate == link_up) { 3645 cas_set_link_modes(cp); 3646 netif_carrier_on(cp->dev); 3647 } 3648} 3649 3650/* Must be invoked under cp->lock. on earlier cassini boards, 3651 * SOFT_0 is tied to PCI reset. we use this to force a pci reset, 3652 * let it settle out, and then restore pci state. 3653 */ 3654static void cas_hard_reset(struct cas *cp) 3655{ 3656 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN); 3657 udelay(20); 3658 pci_restore_state(cp->pdev); 3659} 3660 3661 3662static void cas_global_reset(struct cas *cp, int blkflag) 3663{ 3664 int limit; 3665 3666 /* issue a global reset. don't use RSTOUT. */ 3667 if (blkflag && !CAS_PHY_MII(cp->phy_type)) { 3668 /* For PCS, when the blkflag is set, we should set the 3669 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of 3670 * the last autonegotiation from being cleared. We'll 3671 * need some special handling if the chip is set into a 3672 * loopback mode. 3673 */ 3674 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK), 3675 cp->regs + REG_SW_RESET); 3676 } else { 3677 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET); 3678 } 3679 3680 /* need to wait at least 3ms before polling register */ 3681 mdelay(3); 3682 3683 limit = STOP_TRIES; 3684 while (limit-- > 0) { 3685 u32 val = readl(cp->regs + REG_SW_RESET); 3686 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0) 3687 goto done; 3688 udelay(10); 3689 } 3690 printk(KERN_ERR "%s: sw reset failed.\n", cp->dev->name); 3691 3692done: 3693 /* enable various BIM interrupts */ 3694 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE | 3695 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG); 3696 3697 /* clear out pci error status mask for handled errors. 3698 * we don't deal with DMA counter overflows as they happen 3699 * all the time. 3700 */ 3701 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO | 3702 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE | 3703 PCI_ERR_BIM_DMA_READ), cp->regs + 3704 REG_PCI_ERR_STATUS_MASK); 3705 3706 /* set up for MII by default to address mac rx reset timeout 3707 * issue 3708 */ 3709 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); 3710} 3711 3712static void cas_reset(struct cas *cp, int blkflag) 3713{ 3714 u32 val; 3715 3716 cas_mask_intr(cp); 3717 cas_global_reset(cp, blkflag); 3718 cas_mac_reset(cp); 3719 cas_entropy_reset(cp); 3720 3721 /* disable dma engines. */ 3722 val = readl(cp->regs + REG_TX_CFG); 3723 val &= ~TX_CFG_DMA_EN; 3724 writel(val, cp->regs + REG_TX_CFG); 3725 3726 val = readl(cp->regs + REG_RX_CFG); 3727 val &= ~RX_CFG_DMA_EN; 3728 writel(val, cp->regs + REG_RX_CFG); 3729 3730 /* program header parser */ 3731 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) || 3732 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) { 3733 cas_load_firmware(cp, CAS_HP_FIRMWARE); 3734 } else { 3735 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE); 3736 } 3737 3738 /* clear out error registers */ 3739 spin_lock(&cp->stat_lock[N_TX_RINGS]); 3740 cas_clear_mac_err(cp); 3741 spin_unlock(&cp->stat_lock[N_TX_RINGS]); 3742} 3743 3744/* Shut down the chip, must be called with pm_mutex held. */ 3745static void cas_shutdown(struct cas *cp) 3746{ 3747 unsigned long flags; 3748 3749 /* Make us not-running to avoid timers respawning */ 3750 cp->hw_running = 0; 3751 3752 del_timer_sync(&cp->link_timer); 3753 3754 /* Stop the reset task */ 3755 while (atomic_read(&cp->reset_task_pending)) 3756 schedule(); 3757 /* Actually stop the chip */ 3758 cas_lock_all_save(cp, flags); 3759 cas_reset(cp, 0); 3760 if (cp->cas_flags & CAS_FLAG_SATURN) 3761 cas_phy_powerdown(cp); 3762 cas_unlock_all_restore(cp, flags); 3763} 3764 3765static int cas_change_mtu(struct net_device *dev, int new_mtu) 3766{ 3767 struct cas *cp = netdev_priv(dev); 3768 3769 if (new_mtu < CAS_MIN_MTU || new_mtu > CAS_MAX_MTU) 3770 return -EINVAL; 3771 3772 dev->mtu = new_mtu; 3773 if (!netif_running(dev) || !netif_device_present(dev)) 3774 return 0; 3775 3776 /* let the reset task handle it */ 3777 atomic_inc(&cp->reset_task_pending); 3778 if ((cp->phy_type & CAS_PHY_SERDES)) { 3779 atomic_inc(&cp->reset_task_pending_all); 3780 } else { 3781 atomic_inc(&cp->reset_task_pending_mtu); 3782 } 3783 schedule_work(&cp->reset_task); 3784 3785 flush_scheduled_work(); 3786 return 0; 3787} 3788 3789static void cas_clean_txd(struct cas *cp, int ring) 3790{ 3791 struct cas_tx_desc *txd = cp->init_txds[ring]; 3792 struct sk_buff *skb, **skbs = cp->tx_skbs[ring]; 3793 u64 daddr, dlen; 3794 int i, size; 3795 3796 size = TX_DESC_RINGN_SIZE(ring); 3797 for (i = 0; i < size; i++) { 3798 int frag; 3799 3800 if (skbs[i] == NULL) 3801 continue; 3802 3803 skb = skbs[i]; 3804 skbs[i] = NULL; 3805 3806 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 3807 int ent = i & (size - 1); 3808 3809 /* first buffer is never a tiny buffer and so 3810 * needs to be unmapped. 3811 */ 3812 daddr = le64_to_cpu(txd[ent].buffer); 3813 dlen = CAS_VAL(TX_DESC_BUFLEN, 3814 le64_to_cpu(txd[ent].control)); 3815 pci_unmap_page(cp->pdev, daddr, dlen, 3816 PCI_DMA_TODEVICE); 3817 3818 if (frag != skb_shinfo(skb)->nr_frags) { 3819 i++; 3820 3821 /* next buffer might by a tiny buffer. 3822 * skip past it. 3823 */ 3824 ent = i & (size - 1); 3825 if (cp->tx_tiny_use[ring][ent].used) 3826 i++; 3827 } 3828 } 3829 dev_kfree_skb_any(skb); 3830 } 3831 3832 /* zero out tiny buf usage */ 3833 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring])); 3834} 3835 3836/* freed on close */ 3837static inline void cas_free_rx_desc(struct cas *cp, int ring) 3838{ 3839 cas_page_t **page = cp->rx_pages[ring]; 3840 int i, size; 3841 3842 size = RX_DESC_RINGN_SIZE(ring); 3843 for (i = 0; i < size; i++) { 3844 if (page[i]) { 3845 cas_page_free(cp, page[i]); 3846 page[i] = NULL; 3847 } 3848 } 3849} 3850 3851static void cas_free_rxds(struct cas *cp) 3852{ 3853 int i; 3854 3855 for (i = 0; i < N_RX_DESC_RINGS; i++) 3856 cas_free_rx_desc(cp, i); 3857} 3858 3859/* Must be invoked under cp->lock. */ 3860static void cas_clean_rings(struct cas *cp) 3861{ 3862 int i; 3863 3864 /* need to clean all tx rings */ 3865 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS); 3866 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS); 3867 for (i = 0; i < N_TX_RINGS; i++) 3868 cas_clean_txd(cp, i); 3869 3870 /* zero out init block */ 3871 memset(cp->init_block, 0, sizeof(struct cas_init_block)); 3872 cas_clean_rxds(cp); 3873 cas_clean_rxcs(cp); 3874} 3875 3876/* allocated on open */ 3877static inline int cas_alloc_rx_desc(struct cas *cp, int ring) 3878{ 3879 cas_page_t **page = cp->rx_pages[ring]; 3880 int size, i = 0; 3881 3882 size = RX_DESC_RINGN_SIZE(ring); 3883 for (i = 0; i < size; i++) { 3884 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL) 3885 return -1; 3886 } 3887 return 0; 3888} 3889 3890static int cas_alloc_rxds(struct cas *cp) 3891{ 3892 int i; 3893 3894 for (i = 0; i < N_RX_DESC_RINGS; i++) { 3895 if (cas_alloc_rx_desc(cp, i) < 0) { 3896 cas_free_rxds(cp); 3897 return -1; 3898 } 3899 } 3900 return 0; 3901} 3902 3903static void cas_reset_task(struct work_struct *work) 3904{ 3905 struct cas *cp = container_of(work, struct cas, reset_task); 3906 int pending_all = atomic_read(&cp->reset_task_pending_all); 3907 int pending_spare = atomic_read(&cp->reset_task_pending_spare); 3908 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu); 3909 3910 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) { 3911 /* We can have more tasks scheduled than actually 3912 * needed. 3913 */ 3914 atomic_dec(&cp->reset_task_pending); 3915 return; 3916 } 3917 /* The link went down, we reset the ring, but keep 3918 * DMA stopped. Use this function for reset 3919 * on error as well. 3920 */ 3921 if (cp->hw_running) { 3922 unsigned long flags; 3923 3924 /* Make sure we don't get interrupts or tx packets */ 3925 netif_device_detach(cp->dev); 3926 cas_lock_all_save(cp, flags); 3927 3928 if (cp->opened) { 3929 /* We call cas_spare_recover when we call cas_open. 3930 * but we do not initialize the lists cas_spare_recover 3931 * uses until cas_open is called. 3932 */ 3933 cas_spare_recover(cp, GFP_ATOMIC); 3934 } 3935 /* test => only pending_spare set */ 3936 if (!pending_all && !pending_mtu) 3937 goto done; 3938 /* when pending == CAS_RESET_ALL, the following 3939 * call to cas_init_hw will restart auto negotiation. 3940 * Setting the second argument of cas_reset to 3941 * !(pending == CAS_RESET_ALL) will set this argument 3942 * to 1 (avoiding reinitializing the PHY for the normal 3943 * PCS case) when auto negotiation is not restarted. 3944 */ 3945 cas_reset(cp, !(pending_all > 0)); 3946 if (cp->opened) 3947 cas_clean_rings(cp); 3948 cas_init_hw(cp, (pending_all > 0)); 3949 3950done: 3951 cas_unlock_all_restore(cp, flags); 3952 netif_device_attach(cp->dev); 3953 } 3954 atomic_sub(pending_all, &cp->reset_task_pending_all); 3955 atomic_sub(pending_spare, &cp->reset_task_pending_spare); 3956 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu); 3957 atomic_dec(&cp->reset_task_pending); 3958} 3959 3960static void cas_link_timer(unsigned long data) 3961{ 3962 struct cas *cp = (struct cas *) data; 3963 int mask, pending = 0, reset = 0; 3964 unsigned long flags; 3965 3966 if (link_transition_timeout != 0 && 3967 cp->link_transition_jiffies_valid && 3968 ((jiffies - cp->link_transition_jiffies) > 3969 (link_transition_timeout))) { 3970 cp->link_transition_jiffies_valid = 0; 3971 } 3972 3973 if (!cp->hw_running) 3974 return; 3975 3976 spin_lock_irqsave(&cp->lock, flags); 3977 cas_lock_tx(cp); 3978 cas_entropy_gather(cp); 3979 3980 /* If the link task is still pending, we just 3981 * reschedule the link timer 3982 */ 3983 if (atomic_read(&cp->reset_task_pending_all) || 3984 atomic_read(&cp->reset_task_pending_spare) || 3985 atomic_read(&cp->reset_task_pending_mtu)) 3986 goto done; 3987 3988 /* check for rx cleaning */ 3989 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) { 3990 int i, rmask; 3991 3992 for (i = 0; i < MAX_RX_DESC_RINGS; i++) { 3993 rmask = CAS_FLAG_RXD_POST(i); 3994 if ((mask & rmask) == 0) 3995 continue; 3996 3997 /* post_rxds will do a mod_timer */ 3998 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) { 3999 pending = 1; 4000 continue; 4001 } 4002 cp->cas_flags &= ~rmask; 4003 } 4004 } 4005 4006 if (CAS_PHY_MII(cp->phy_type)) { 4007 u16 bmsr; 4008 cas_mif_poll(cp, 0); 4009 bmsr = cas_phy_read(cp, MII_BMSR); 4010 /* WTZ: Solaris driver reads this twice, but that 4011 * may be due to the PCS case and the use of a 4012 * common implementation. Read it twice here to be 4013 * safe. 4014 */ 4015 bmsr = cas_phy_read(cp, MII_BMSR); 4016 cas_mif_poll(cp, 1); 4017 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */ 4018 reset = cas_mii_link_check(cp, bmsr); 4019 } else { 4020 reset = cas_pcs_link_check(cp); 4021 } 4022 4023 if (reset) 4024 goto done; 4025 4026 /* check for tx state machine confusion */ 4027 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) { 4028 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE); 4029 u32 wptr, rptr; 4030 int tlm = CAS_VAL(MAC_SM_TLM, val); 4031 4032 if (((tlm == 0x5) || (tlm == 0x3)) && 4033 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) { 4034 if (netif_msg_tx_err(cp)) 4035 printk(KERN_DEBUG "%s: tx err: " 4036 "MAC_STATE[%08x]\n", 4037 cp->dev->name, val); 4038 reset = 1; 4039 goto done; 4040 } 4041 4042 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT); 4043 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); 4044 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR); 4045 if ((val == 0) && (wptr != rptr)) { 4046 if (netif_msg_tx_err(cp)) 4047 printk(KERN_DEBUG "%s: tx err: " 4048 "TX_FIFO[%08x:%08x:%08x]\n", 4049 cp->dev->name, val, wptr, rptr); 4050 reset = 1; 4051 } 4052 4053 if (reset) 4054 cas_hard_reset(cp); 4055 } 4056 4057done: 4058 if (reset) { 4059 atomic_inc(&cp->reset_task_pending); 4060 atomic_inc(&cp->reset_task_pending_all); 4061 schedule_work(&cp->reset_task); 4062 } 4063 4064 if (!pending) 4065 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 4066 cas_unlock_tx(cp); 4067 spin_unlock_irqrestore(&cp->lock, flags); 4068} 4069 4070/* tiny buffers are used to avoid target abort issues with 4071 * older cassini's 4072 */ 4073static void cas_tx_tiny_free(struct cas *cp) 4074{ 4075 struct pci_dev *pdev = cp->pdev; 4076 int i; 4077 4078 for (i = 0; i < N_TX_RINGS; i++) { 4079 if (!cp->tx_tiny_bufs[i]) 4080 continue; 4081 4082 pci_free_consistent(pdev, TX_TINY_BUF_BLOCK, 4083 cp->tx_tiny_bufs[i], 4084 cp->tx_tiny_dvma[i]); 4085 cp->tx_tiny_bufs[i] = NULL; 4086 } 4087} 4088 4089static int cas_tx_tiny_alloc(struct cas *cp) 4090{ 4091 struct pci_dev *pdev = cp->pdev; 4092 int i; 4093 4094 for (i = 0; i < N_TX_RINGS; i++) { 4095 cp->tx_tiny_bufs[i] = 4096 pci_alloc_consistent(pdev, TX_TINY_BUF_BLOCK, 4097 &cp->tx_tiny_dvma[i]); 4098 if (!cp->tx_tiny_bufs[i]) { 4099 cas_tx_tiny_free(cp); 4100 return -1; 4101 } 4102 } 4103 return 0; 4104} 4105 4106 4107static int cas_open(struct net_device *dev) 4108{ 4109 struct cas *cp = netdev_priv(dev); 4110 int hw_was_up, err; 4111 unsigned long flags; 4112 4113 mutex_lock(&cp->pm_mutex); 4114 4115 hw_was_up = cp->hw_running; 4116 4117 /* The power-management mutex protects the hw_running 4118 * etc. state so it is safe to do this bit without cp->lock 4119 */ 4120 if (!cp->hw_running) { 4121 /* Reset the chip */ 4122 cas_lock_all_save(cp, flags); 4123 /* We set the second arg to cas_reset to zero 4124 * because cas_init_hw below will have its second 4125 * argument set to non-zero, which will force 4126 * autonegotiation to start. 4127 */ 4128 cas_reset(cp, 0); 4129 cp->hw_running = 1; 4130 cas_unlock_all_restore(cp, flags); 4131 } 4132 4133 if (cas_tx_tiny_alloc(cp) < 0) 4134 return -ENOMEM; 4135 4136 /* alloc rx descriptors */ 4137 err = -ENOMEM; 4138 if (cas_alloc_rxds(cp) < 0) 4139 goto err_tx_tiny; 4140 4141 /* allocate spares */ 4142 cas_spare_init(cp); 4143 cas_spare_recover(cp, GFP_KERNEL); 4144 4145 /* We can now request the interrupt as we know it's masked 4146 * on the controller. cassini+ has up to 4 interrupts 4147 * that can be used, but you need to do explicit pci interrupt 4148 * mapping to expose them 4149 */ 4150 if (request_irq(cp->pdev->irq, cas_interrupt, 4151 IRQF_SHARED, dev->name, (void *) dev)) { 4152 printk(KERN_ERR "%s: failed to request irq !\n", 4153 cp->dev->name); 4154 err = -EAGAIN; 4155 goto err_spare; 4156 } 4157 4158 /* init hw */ 4159 cas_lock_all_save(cp, flags); 4160 cas_clean_rings(cp); 4161 cas_init_hw(cp, !hw_was_up); 4162 cp->opened = 1; 4163 cas_unlock_all_restore(cp, flags); 4164 4165 netif_start_queue(dev); 4166 mutex_unlock(&cp->pm_mutex); 4167 return 0; 4168 4169err_spare: 4170 cas_spare_free(cp); 4171 cas_free_rxds(cp); 4172err_tx_tiny: 4173 cas_tx_tiny_free(cp); 4174 mutex_unlock(&cp->pm_mutex); 4175 return err; 4176} 4177 4178static int cas_close(struct net_device *dev) 4179{ 4180 unsigned long flags; 4181 struct cas *cp = netdev_priv(dev); 4182 4183 /* Make sure we don't get distracted by suspend/resume */ 4184 mutex_lock(&cp->pm_mutex); 4185 4186 netif_stop_queue(dev); 4187 4188 /* Stop traffic, mark us closed */ 4189 cas_lock_all_save(cp, flags); 4190 cp->opened = 0; 4191 cas_reset(cp, 0); 4192 cas_phy_init(cp); 4193 cas_begin_auto_negotiation(cp, NULL); 4194 cas_clean_rings(cp); 4195 cas_unlock_all_restore(cp, flags); 4196 4197 free_irq(cp->pdev->irq, (void *) dev); 4198 cas_spare_free(cp); 4199 cas_free_rxds(cp); 4200 cas_tx_tiny_free(cp); 4201 mutex_unlock(&cp->pm_mutex); 4202 return 0; 4203} 4204 4205static struct { 4206 const char name[ETH_GSTRING_LEN]; 4207} ethtool_cassini_statnames[] = { 4208 {"collisions"}, 4209 {"rx_bytes"}, 4210 {"rx_crc_errors"}, 4211 {"rx_dropped"}, 4212 {"rx_errors"}, 4213 {"rx_fifo_errors"}, 4214 {"rx_frame_errors"}, 4215 {"rx_length_errors"}, 4216 {"rx_over_errors"}, 4217 {"rx_packets"}, 4218 {"tx_aborted_errors"}, 4219 {"tx_bytes"}, 4220 {"tx_dropped"}, 4221 {"tx_errors"}, 4222 {"tx_fifo_errors"}, 4223 {"tx_packets"} 4224}; 4225#define CAS_NUM_STAT_KEYS (sizeof(ethtool_cassini_statnames)/ETH_GSTRING_LEN) 4226 4227static struct { 4228 const int offsets; /* neg. values for 2nd arg to cas_read_phy */ 4229} ethtool_register_table[] = { 4230 {-MII_BMSR}, 4231 {-MII_BMCR}, 4232 {REG_CAWR}, 4233 {REG_INF_BURST}, 4234 {REG_BIM_CFG}, 4235 {REG_RX_CFG}, 4236 {REG_HP_CFG}, 4237 {REG_MAC_TX_CFG}, 4238 {REG_MAC_RX_CFG}, 4239 {REG_MAC_CTRL_CFG}, 4240 {REG_MAC_XIF_CFG}, 4241 {REG_MIF_CFG}, 4242 {REG_PCS_CFG}, 4243 {REG_SATURN_PCFG}, 4244 {REG_PCS_MII_STATUS}, 4245 {REG_PCS_STATE_MACHINE}, 4246 {REG_MAC_COLL_EXCESS}, 4247 {REG_MAC_COLL_LATE} 4248}; 4249#define CAS_REG_LEN (sizeof(ethtool_register_table)/sizeof(int)) 4250#define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN) 4251 4252static void cas_read_regs(struct cas *cp, u8 *ptr, int len) 4253{ 4254 u8 *p; 4255 int i; 4256 unsigned long flags; 4257 4258 spin_lock_irqsave(&cp->lock, flags); 4259 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) { 4260 u16 hval; 4261 u32 val; 4262 if (ethtool_register_table[i].offsets < 0) { 4263 hval = cas_phy_read(cp, 4264 -ethtool_register_table[i].offsets); 4265 val = hval; 4266 } else { 4267 val= readl(cp->regs+ethtool_register_table[i].offsets); 4268 } 4269 memcpy(p, (u8 *)&val, sizeof(u32)); 4270 } 4271 spin_unlock_irqrestore(&cp->lock, flags); 4272} 4273 4274static struct net_device_stats *cas_get_stats(struct net_device *dev) 4275{ 4276 struct cas *cp = netdev_priv(dev); 4277 struct net_device_stats *stats = cp->net_stats; 4278 unsigned long flags; 4279 int i; 4280 unsigned long tmp; 4281 4282 /* we collate all of the stats into net_stats[N_TX_RING] */ 4283 if (!cp->hw_running) 4284 return stats + N_TX_RINGS; 4285 4286 /* collect outstanding stats */ 4287 /* WTZ: the Cassini spec gives these as 16 bit counters but 4288 * stored in 32-bit words. Added a mask of 0xffff to be safe, 4289 * in case the chip somehow puts any garbage in the other bits. 4290 * Also, counter usage didn't seem to mach what Adrian did 4291 * in the parts of the code that set these quantities. Made 4292 * that consistent. 4293 */ 4294 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags); 4295 stats[N_TX_RINGS].rx_crc_errors += 4296 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff; 4297 stats[N_TX_RINGS].rx_frame_errors += 4298 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff; 4299 stats[N_TX_RINGS].rx_length_errors += 4300 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff; 4301 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) + 4302 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff); 4303 stats[N_TX_RINGS].tx_aborted_errors += tmp; 4304 stats[N_TX_RINGS].collisions += 4305 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff); 4306 cas_clear_mac_err(cp); 4307 4308 /* saved bits that are unique to ring 0 */ 4309 spin_lock(&cp->stat_lock[0]); 4310 stats[N_TX_RINGS].collisions += stats[0].collisions; 4311 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors; 4312 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors; 4313 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors; 4314 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors; 4315 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors; 4316 spin_unlock(&cp->stat_lock[0]); 4317 4318 for (i = 0; i < N_TX_RINGS; i++) { 4319 spin_lock(&cp->stat_lock[i]); 4320 stats[N_TX_RINGS].rx_length_errors += 4321 stats[i].rx_length_errors; 4322 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors; 4323 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets; 4324 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets; 4325 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes; 4326 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes; 4327 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors; 4328 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors; 4329 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped; 4330 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped; 4331 memset(stats + i, 0, sizeof(struct net_device_stats)); 4332 spin_unlock(&cp->stat_lock[i]); 4333 } 4334 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags); 4335 return stats + N_TX_RINGS; 4336} 4337 4338 4339static void cas_set_multicast(struct net_device *dev) 4340{ 4341 struct cas *cp = netdev_priv(dev); 4342 u32 rxcfg, rxcfg_new; 4343 unsigned long flags; 4344 int limit = STOP_TRIES; 4345 4346 if (!cp->hw_running) 4347 return; 4348 4349 spin_lock_irqsave(&cp->lock, flags); 4350 rxcfg = readl(cp->regs + REG_MAC_RX_CFG); 4351 4352 /* disable RX MAC and wait for completion */ 4353 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 4354 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) { 4355 if (!limit--) 4356 break; 4357 udelay(10); 4358 } 4359 4360 /* disable hash filter and wait for completion */ 4361 limit = STOP_TRIES; 4362 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN); 4363 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 4364 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) { 4365 if (!limit--) 4366 break; 4367 udelay(10); 4368 } 4369 4370 /* program hash filters */ 4371 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp); 4372 rxcfg |= rxcfg_new; 4373 writel(rxcfg, cp->regs + REG_MAC_RX_CFG); 4374 spin_unlock_irqrestore(&cp->lock, flags); 4375} 4376 4377static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 4378{ 4379 struct cas *cp = netdev_priv(dev); 4380 strncpy(info->driver, DRV_MODULE_NAME, ETHTOOL_BUSINFO_LEN); 4381 strncpy(info->version, DRV_MODULE_VERSION, ETHTOOL_BUSINFO_LEN); 4382 info->fw_version[0] = '\0'; 4383 strncpy(info->bus_info, pci_name(cp->pdev), ETHTOOL_BUSINFO_LEN); 4384 info->regdump_len = cp->casreg_len < CAS_MAX_REGS ? 4385 cp->casreg_len : CAS_MAX_REGS; 4386 info->n_stats = CAS_NUM_STAT_KEYS; 4387} 4388 4389static int cas_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 4390{ 4391 struct cas *cp = netdev_priv(dev); 4392 u16 bmcr; 4393 int full_duplex, speed, pause; 4394 unsigned long flags; 4395 enum link_state linkstate = link_up; 4396 4397 cmd->advertising = 0; 4398 cmd->supported = SUPPORTED_Autoneg; 4399 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 4400 cmd->supported |= SUPPORTED_1000baseT_Full; 4401 cmd->advertising |= ADVERTISED_1000baseT_Full; 4402 } 4403 4404 /* Record PHY settings if HW is on. */ 4405 spin_lock_irqsave(&cp->lock, flags); 4406 bmcr = 0; 4407 linkstate = cp->lstate; 4408 if (CAS_PHY_MII(cp->phy_type)) { 4409 cmd->port = PORT_MII; 4410 cmd->transceiver = (cp->cas_flags & CAS_FLAG_SATURN) ? 4411 XCVR_INTERNAL : XCVR_EXTERNAL; 4412 cmd->phy_address = cp->phy_addr; 4413 cmd->advertising |= ADVERTISED_TP | ADVERTISED_MII | 4414 ADVERTISED_10baseT_Half | 4415 ADVERTISED_10baseT_Full | 4416 ADVERTISED_100baseT_Half | 4417 ADVERTISED_100baseT_Full; 4418 4419 cmd->supported |= 4420 (SUPPORTED_10baseT_Half | 4421 SUPPORTED_10baseT_Full | 4422 SUPPORTED_100baseT_Half | 4423 SUPPORTED_100baseT_Full | 4424 SUPPORTED_TP | SUPPORTED_MII); 4425 4426 if (cp->hw_running) { 4427 cas_mif_poll(cp, 0); 4428 bmcr = cas_phy_read(cp, MII_BMCR); 4429 cas_read_mii_link_mode(cp, &full_duplex, 4430 &speed, &pause); 4431 cas_mif_poll(cp, 1); 4432 } 4433 4434 } else { 4435 cmd->port = PORT_FIBRE; 4436 cmd->transceiver = XCVR_INTERNAL; 4437 cmd->phy_address = 0; 4438 cmd->supported |= SUPPORTED_FIBRE; 4439 cmd->advertising |= ADVERTISED_FIBRE; 4440 4441 if (cp->hw_running) { 4442 /* pcs uses the same bits as mii */ 4443 bmcr = readl(cp->regs + REG_PCS_MII_CTRL); 4444 cas_read_pcs_link_mode(cp, &full_duplex, 4445 &speed, &pause); 4446 } 4447 } 4448 spin_unlock_irqrestore(&cp->lock, flags); 4449 4450 if (bmcr & BMCR_ANENABLE) { 4451 cmd->advertising |= ADVERTISED_Autoneg; 4452 cmd->autoneg = AUTONEG_ENABLE; 4453 cmd->speed = ((speed == 10) ? 4454 SPEED_10 : 4455 ((speed == 1000) ? 4456 SPEED_1000 : SPEED_100)); 4457 cmd->duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 4458 } else { 4459 cmd->autoneg = AUTONEG_DISABLE; 4460 cmd->speed = 4461 (bmcr & CAS_BMCR_SPEED1000) ? 4462 SPEED_1000 : 4463 ((bmcr & BMCR_SPEED100) ? SPEED_100: 4464 SPEED_10); 4465 cmd->duplex = 4466 (bmcr & BMCR_FULLDPLX) ? 4467 DUPLEX_FULL : DUPLEX_HALF; 4468 } 4469 if (linkstate != link_up) { 4470 /* Force these to "unknown" if the link is not up and 4471 * autonogotiation in enabled. We can set the link 4472 * speed to 0, but not cmd->duplex, 4473 * because its legal values are 0 and 1. Ethtool will 4474 * print the value reported in parentheses after the 4475 * word "Unknown" for unrecognized values. 4476 * 4477 * If in forced mode, we report the speed and duplex 4478 * settings that we configured. 4479 */ 4480 if (cp->link_cntl & BMCR_ANENABLE) { 4481 cmd->speed = 0; 4482 cmd->duplex = 0xff; 4483 } else { 4484 cmd->speed = SPEED_10; 4485 if (cp->link_cntl & BMCR_SPEED100) { 4486 cmd->speed = SPEED_100; 4487 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) { 4488 cmd->speed = SPEED_1000; 4489 } 4490 cmd->duplex = (cp->link_cntl & BMCR_FULLDPLX)? 4491 DUPLEX_FULL : DUPLEX_HALF; 4492 } 4493 } 4494 return 0; 4495} 4496 4497static int cas_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 4498{ 4499 struct cas *cp = netdev_priv(dev); 4500 unsigned long flags; 4501 4502 /* Verify the settings we care about. */ 4503 if (cmd->autoneg != AUTONEG_ENABLE && 4504 cmd->autoneg != AUTONEG_DISABLE) 4505 return -EINVAL; 4506 4507 if (cmd->autoneg == AUTONEG_DISABLE && 4508 ((cmd->speed != SPEED_1000 && 4509 cmd->speed != SPEED_100 && 4510 cmd->speed != SPEED_10) || 4511 (cmd->duplex != DUPLEX_HALF && 4512 cmd->duplex != DUPLEX_FULL))) 4513 return -EINVAL; 4514 4515 /* Apply settings and restart link process. */ 4516 spin_lock_irqsave(&cp->lock, flags); 4517 cas_begin_auto_negotiation(cp, cmd); 4518 spin_unlock_irqrestore(&cp->lock, flags); 4519 return 0; 4520} 4521 4522static int cas_nway_reset(struct net_device *dev) 4523{ 4524 struct cas *cp = netdev_priv(dev); 4525 unsigned long flags; 4526 4527 if ((cp->link_cntl & BMCR_ANENABLE) == 0) 4528 return -EINVAL; 4529 4530 /* Restart link process. */ 4531 spin_lock_irqsave(&cp->lock, flags); 4532 cas_begin_auto_negotiation(cp, NULL); 4533 spin_unlock_irqrestore(&cp->lock, flags); 4534 4535 return 0; 4536} 4537 4538static u32 cas_get_link(struct net_device *dev) 4539{ 4540 struct cas *cp = netdev_priv(dev); 4541 return cp->lstate == link_up; 4542} 4543 4544static u32 cas_get_msglevel(struct net_device *dev) 4545{ 4546 struct cas *cp = netdev_priv(dev); 4547 return cp->msg_enable; 4548} 4549 4550static void cas_set_msglevel(struct net_device *dev, u32 value) 4551{ 4552 struct cas *cp = netdev_priv(dev); 4553 cp->msg_enable = value; 4554} 4555 4556static int cas_get_regs_len(struct net_device *dev) 4557{ 4558 struct cas *cp = netdev_priv(dev); 4559 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS; 4560} 4561 4562static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4563 void *p) 4564{ 4565 struct cas *cp = netdev_priv(dev); 4566 regs->version = 0; 4567 /* cas_read_regs handles locks (cp->lock). */ 4568 cas_read_regs(cp, p, regs->len / sizeof(u32)); 4569} 4570 4571static int cas_get_stats_count(struct net_device *dev) 4572{ 4573 return CAS_NUM_STAT_KEYS; 4574} 4575 4576static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4577{ 4578 memcpy(data, ðtool_cassini_statnames, 4579 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN); 4580} 4581 4582static void cas_get_ethtool_stats(struct net_device *dev, 4583 struct ethtool_stats *estats, u64 *data) 4584{ 4585 struct cas *cp = netdev_priv(dev); 4586 struct net_device_stats *stats = cas_get_stats(cp->dev); 4587 int i = 0; 4588 data[i++] = stats->collisions; 4589 data[i++] = stats->rx_bytes; 4590 data[i++] = stats->rx_crc_errors; 4591 data[i++] = stats->rx_dropped; 4592 data[i++] = stats->rx_errors; 4593 data[i++] = stats->rx_fifo_errors; 4594 data[i++] = stats->rx_frame_errors; 4595 data[i++] = stats->rx_length_errors; 4596 data[i++] = stats->rx_over_errors; 4597 data[i++] = stats->rx_packets; 4598 data[i++] = stats->tx_aborted_errors; 4599 data[i++] = stats->tx_bytes; 4600 data[i++] = stats->tx_dropped; 4601 data[i++] = stats->tx_errors; 4602 data[i++] = stats->tx_fifo_errors; 4603 data[i++] = stats->tx_packets; 4604 BUG_ON(i != CAS_NUM_STAT_KEYS); 4605} 4606 4607static const struct ethtool_ops cas_ethtool_ops = { 4608 .get_drvinfo = cas_get_drvinfo, 4609 .get_settings = cas_get_settings, 4610 .set_settings = cas_set_settings, 4611 .nway_reset = cas_nway_reset, 4612 .get_link = cas_get_link, 4613 .get_msglevel = cas_get_msglevel, 4614 .set_msglevel = cas_set_msglevel, 4615 .get_regs_len = cas_get_regs_len, 4616 .get_regs = cas_get_regs, 4617 .get_stats_count = cas_get_stats_count, 4618 .get_strings = cas_get_strings, 4619 .get_ethtool_stats = cas_get_ethtool_stats, 4620}; 4621 4622static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4623{ 4624 struct cas *cp = netdev_priv(dev); 4625 struct mii_ioctl_data *data = if_mii(ifr); 4626 unsigned long flags; 4627 int rc = -EOPNOTSUPP; 4628 4629 /* Hold the PM mutex while doing ioctl's or we may collide 4630 * with open/close and power management and oops. 4631 */ 4632 mutex_lock(&cp->pm_mutex); 4633 switch (cmd) { 4634 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 4635 data->phy_id = cp->phy_addr; 4636 /* Fallthrough... */ 4637 4638 case SIOCGMIIREG: /* Read MII PHY register. */ 4639 spin_lock_irqsave(&cp->lock, flags); 4640 cas_mif_poll(cp, 0); 4641 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f); 4642 cas_mif_poll(cp, 1); 4643 spin_unlock_irqrestore(&cp->lock, flags); 4644 rc = 0; 4645 break; 4646 4647 case SIOCSMIIREG: /* Write MII PHY register. */ 4648 if (!capable(CAP_NET_ADMIN)) { 4649 rc = -EPERM; 4650 break; 4651 } 4652 spin_lock_irqsave(&cp->lock, flags); 4653 cas_mif_poll(cp, 0); 4654 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in); 4655 cas_mif_poll(cp, 1); 4656 spin_unlock_irqrestore(&cp->lock, flags); 4657 break; 4658 default: 4659 break; 4660 }; 4661 4662 mutex_unlock(&cp->pm_mutex); 4663 return rc; 4664} 4665 4666static int __devinit cas_init_one(struct pci_dev *pdev, 4667 const struct pci_device_id *ent) 4668{ 4669 static int cas_version_printed = 0; 4670 unsigned long casreg_len; 4671 struct net_device *dev; 4672 struct cas *cp; 4673 int i, err, pci_using_dac; 4674 u16 pci_cmd; 4675 u8 orig_cacheline_size = 0, cas_cacheline_size = 0; 4676 4677 if (cas_version_printed++ == 0) 4678 printk(KERN_INFO "%s", version); 4679 4680 err = pci_enable_device(pdev); 4681 if (err) { 4682 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n"); 4683 return err; 4684 } 4685 4686 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 4687 dev_err(&pdev->dev, "Cannot find proper PCI device " 4688 "base address, aborting.\n"); 4689 err = -ENODEV; 4690 goto err_out_disable_pdev; 4691 } 4692 4693 dev = alloc_etherdev(sizeof(*cp)); 4694 if (!dev) { 4695 dev_err(&pdev->dev, "Etherdev alloc failed, aborting.\n"); 4696 err = -ENOMEM; 4697 goto err_out_disable_pdev; 4698 } 4699 SET_MODULE_OWNER(dev); 4700 SET_NETDEV_DEV(dev, &pdev->dev); 4701 4702 err = pci_request_regions(pdev, dev->name); 4703 if (err) { 4704 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n"); 4705 goto err_out_free_netdev; 4706 } 4707 pci_set_master(pdev); 4708 4709 /* we must always turn on parity response or else parity 4710 * doesn't get generated properly. disable SERR/PERR as well. 4711 * in addition, we want to turn MWI on. 4712 */ 4713 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4714 pci_cmd &= ~PCI_COMMAND_SERR; 4715 pci_cmd |= PCI_COMMAND_PARITY; 4716 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4717 if (pci_set_mwi(pdev)) 4718 printk(KERN_WARNING PFX "Could not enable MWI for %s\n", 4719 pci_name(pdev)); 4720 4721 /* 4722 * On some architectures, the default cache line size set 4723 * by pci_set_mwi reduces perforamnce. We have to increase 4724 * it for this case. To start, we'll print some configuration 4725 * data. 4726 */ 4727 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, 4728 &orig_cacheline_size); 4729 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) { 4730 cas_cacheline_size = 4731 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ? 4732 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES; 4733 if (pci_write_config_byte(pdev, 4734 PCI_CACHE_LINE_SIZE, 4735 cas_cacheline_size)) { 4736 dev_err(&pdev->dev, "Could not set PCI cache " 4737 "line size\n"); 4738 goto err_write_cacheline; 4739 } 4740 } 4741 4742 4743 /* Configure DMA attributes. */ 4744 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { 4745 pci_using_dac = 1; 4746 err = pci_set_consistent_dma_mask(pdev, 4747 DMA_64BIT_MASK); 4748 if (err < 0) { 4749 dev_err(&pdev->dev, "Unable to obtain 64-bit DMA " 4750 "for consistent allocations\n"); 4751 goto err_out_free_res; 4752 } 4753 4754 } else { 4755 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); 4756 if (err) { 4757 dev_err(&pdev->dev, "No usable DMA configuration, " 4758 "aborting.\n"); 4759 goto err_out_free_res; 4760 } 4761 pci_using_dac = 0; 4762 } 4763 4764 casreg_len = pci_resource_len(pdev, 0); 4765 4766 cp = netdev_priv(dev); 4767 cp->pdev = pdev; 4768 /* A value of 0 indicates we never explicitly set it */ 4769 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0; 4770 cp->dev = dev; 4771 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE : 4772 cassini_debug; 4773 4774 cp->link_transition = LINK_TRANSITION_UNKNOWN; 4775 cp->link_transition_jiffies_valid = 0; 4776 4777 spin_lock_init(&cp->lock); 4778 spin_lock_init(&cp->rx_inuse_lock); 4779 spin_lock_init(&cp->rx_spare_lock); 4780 for (i = 0; i < N_TX_RINGS; i++) { 4781 spin_lock_init(&cp->stat_lock[i]); 4782 spin_lock_init(&cp->tx_lock[i]); 4783 } 4784 spin_lock_init(&cp->stat_lock[N_TX_RINGS]); 4785 mutex_init(&cp->pm_mutex); 4786 4787 init_timer(&cp->link_timer); 4788 cp->link_timer.function = cas_link_timer; 4789 cp->link_timer.data = (unsigned long) cp; 4790 4791 /* Just in case the implementation of atomic operations 4792 * change so that an explicit initialization is necessary. 4793 */ 4794 atomic_set(&cp->reset_task_pending, 0); 4795 atomic_set(&cp->reset_task_pending_all, 0); 4796 atomic_set(&cp->reset_task_pending_spare, 0); 4797 atomic_set(&cp->reset_task_pending_mtu, 0); 4798 INIT_WORK(&cp->reset_task, cas_reset_task); 4799 4800 /* Default link parameters */ 4801 if (link_mode >= 0 && link_mode <= 6) 4802 cp->link_cntl = link_modes[link_mode]; 4803 else 4804 cp->link_cntl = BMCR_ANENABLE; 4805 cp->lstate = link_down; 4806 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 4807 netif_carrier_off(cp->dev); 4808 cp->timer_ticks = 0; 4809 4810 /* give us access to cassini registers */ 4811 cp->regs = pci_iomap(pdev, 0, casreg_len); 4812 if (cp->regs == 0UL) { 4813 dev_err(&pdev->dev, "Cannot map device registers, aborting.\n"); 4814 goto err_out_free_res; 4815 } 4816 cp->casreg_len = casreg_len; 4817 4818 pci_save_state(pdev); 4819 cas_check_pci_invariants(cp); 4820 cas_hard_reset(cp); 4821 cas_reset(cp, 0); 4822 if (cas_check_invariants(cp)) 4823 goto err_out_iounmap; 4824 4825 cp->init_block = (struct cas_init_block *) 4826 pci_alloc_consistent(pdev, sizeof(struct cas_init_block), 4827 &cp->block_dvma); 4828 if (!cp->init_block) { 4829 dev_err(&pdev->dev, "Cannot allocate init block, aborting.\n"); 4830 goto err_out_iounmap; 4831 } 4832 4833 for (i = 0; i < N_TX_RINGS; i++) 4834 cp->init_txds[i] = cp->init_block->txds[i]; 4835 4836 for (i = 0; i < N_RX_DESC_RINGS; i++) 4837 cp->init_rxds[i] = cp->init_block->rxds[i]; 4838 4839 for (i = 0; i < N_RX_COMP_RINGS; i++) 4840 cp->init_rxcs[i] = cp->init_block->rxcs[i]; 4841 4842 for (i = 0; i < N_RX_FLOWS; i++) 4843 skb_queue_head_init(&cp->rx_flows[i]); 4844 4845 dev->open = cas_open; 4846 dev->stop = cas_close; 4847 dev->hard_start_xmit = cas_start_xmit; 4848 dev->get_stats = cas_get_stats; 4849 dev->set_multicast_list = cas_set_multicast; 4850 dev->do_ioctl = cas_ioctl; 4851 dev->ethtool_ops = &cas_ethtool_ops; 4852 dev->tx_timeout = cas_tx_timeout; 4853 dev->watchdog_timeo = CAS_TX_TIMEOUT; 4854 dev->change_mtu = cas_change_mtu; 4855#ifdef USE_NAPI 4856 dev->poll = cas_poll; 4857 dev->weight = 64; 4858#endif 4859#ifdef CONFIG_NET_POLL_CONTROLLER 4860 dev->poll_controller = cas_netpoll; 4861#endif 4862 dev->irq = pdev->irq; 4863 dev->dma = 0; 4864 4865 /* Cassini features. */ 4866 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0) 4867 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; 4868 4869 if (pci_using_dac) 4870 dev->features |= NETIF_F_HIGHDMA; 4871 4872 if (register_netdev(dev)) { 4873 dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); 4874 goto err_out_free_consistent; 4875 } 4876 4877 i = readl(cp->regs + REG_BIM_CFG); 4878 printk(KERN_INFO "%s: Sun Cassini%s (%sbit/%sMHz PCI/%s) " 4879 "Ethernet[%d] ", dev->name, 4880 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "", 4881 (i & BIM_CFG_32BIT) ? "32" : "64", 4882 (i & BIM_CFG_66MHZ) ? "66" : "33", 4883 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq); 4884 4885 for (i = 0; i < 6; i++) 4886 printk("%2.2x%c", dev->dev_addr[i], 4887 i == 5 ? ' ' : ':'); 4888 printk("\n"); 4889 4890 pci_set_drvdata(pdev, dev); 4891 cp->hw_running = 1; 4892 cas_entropy_reset(cp); 4893 cas_phy_init(cp); 4894 cas_begin_auto_negotiation(cp, NULL); 4895 return 0; 4896 4897err_out_free_consistent: 4898 pci_free_consistent(pdev, sizeof(struct cas_init_block), 4899 cp->init_block, cp->block_dvma); 4900 4901err_out_iounmap: 4902 mutex_lock(&cp->pm_mutex); 4903 if (cp->hw_running) 4904 cas_shutdown(cp); 4905 mutex_unlock(&cp->pm_mutex); 4906 4907 pci_iounmap(pdev, cp->regs); 4908 4909 4910err_out_free_res: 4911 pci_release_regions(pdev); 4912 4913err_write_cacheline: 4914 /* Try to restore it in case the error occured after we 4915 * set it. 4916 */ 4917 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size); 4918 4919err_out_free_netdev: 4920 free_netdev(dev); 4921 4922err_out_disable_pdev: 4923 pci_disable_device(pdev); 4924 pci_set_drvdata(pdev, NULL); 4925 return -ENODEV; 4926} 4927 4928static void __devexit cas_remove_one(struct pci_dev *pdev) 4929{ 4930 struct net_device *dev = pci_get_drvdata(pdev); 4931 struct cas *cp; 4932 if (!dev) 4933 return; 4934 4935 cp = netdev_priv(dev); 4936 unregister_netdev(dev); 4937 4938 mutex_lock(&cp->pm_mutex); 4939 flush_scheduled_work(); 4940 if (cp->hw_running) 4941 cas_shutdown(cp); 4942 mutex_unlock(&cp->pm_mutex); 4943 4944 if (cp->orig_cacheline_size) { 4945 /* Restore the cache line size if we had modified 4946 * it. 4947 */ 4948 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 4949 cp->orig_cacheline_size); 4950 } 4951 pci_free_consistent(pdev, sizeof(struct cas_init_block), 4952 cp->init_block, cp->block_dvma); 4953 pci_iounmap(pdev, cp->regs); 4954 free_netdev(dev); 4955 pci_release_regions(pdev); 4956 pci_disable_device(pdev); 4957 pci_set_drvdata(pdev, NULL); 4958} 4959 4960#ifdef CONFIG_PM 4961static int cas_suspend(struct pci_dev *pdev, pm_message_t state) 4962{ 4963 struct net_device *dev = pci_get_drvdata(pdev); 4964 struct cas *cp = netdev_priv(dev); 4965 unsigned long flags; 4966 4967 mutex_lock(&cp->pm_mutex); 4968 4969 /* If the driver is opened, we stop the DMA */ 4970 if (cp->opened) { 4971 netif_device_detach(dev); 4972 4973 cas_lock_all_save(cp, flags); 4974 4975 /* We can set the second arg of cas_reset to 0 4976 * because on resume, we'll call cas_init_hw with 4977 * its second arg set so that autonegotiation is 4978 * restarted. 4979 */ 4980 cas_reset(cp, 0); 4981 cas_clean_rings(cp); 4982 cas_unlock_all_restore(cp, flags); 4983 } 4984 4985 if (cp->hw_running) 4986 cas_shutdown(cp); 4987 mutex_unlock(&cp->pm_mutex); 4988 4989 return 0; 4990} 4991 4992static int cas_resume(struct pci_dev *pdev) 4993{ 4994 struct net_device *dev = pci_get_drvdata(pdev); 4995 struct cas *cp = netdev_priv(dev); 4996 4997 printk(KERN_INFO "%s: resuming\n", dev->name); 4998 4999 mutex_lock(&cp->pm_mutex); 5000 cas_hard_reset(cp); 5001 if (cp->opened) { 5002 unsigned long flags; 5003 cas_lock_all_save(cp, flags); 5004 cas_reset(cp, 0); 5005 cp->hw_running = 1; 5006 cas_clean_rings(cp); 5007 cas_init_hw(cp, 1); 5008 cas_unlock_all_restore(cp, flags); 5009 5010 netif_device_attach(dev); 5011 } 5012 mutex_unlock(&cp->pm_mutex); 5013 return 0; 5014} 5015#endif /* CONFIG_PM */ 5016 5017static struct pci_driver cas_driver = { 5018 .name = DRV_MODULE_NAME, 5019 .id_table = cas_pci_tbl, 5020 .probe = cas_init_one, 5021 .remove = __devexit_p(cas_remove_one), 5022#ifdef CONFIG_PM 5023 .suspend = cas_suspend, 5024 .resume = cas_resume 5025#endif 5026}; 5027 5028static int __init cas_init(void) 5029{ 5030 if (linkdown_timeout > 0) 5031 link_transition_timeout = linkdown_timeout * HZ; 5032 else 5033 link_transition_timeout = 0; 5034 5035 return pci_register_driver(&cas_driver); 5036} 5037 5038static void __exit cas_cleanup(void) 5039{ 5040 pci_unregister_driver(&cas_driver); 5041} 5042 5043module_init(cas_init); 5044module_exit(cas_cleanup); 5045