Searched refs:MDIO_DEV_TXPLL (Results 1 - 2 of 2) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/include/
H A Dpcie_core.h310 #define MDIO_DEV_TXPLL 0x808 /* TXPLL register block idx */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/shared/
H A Dnicpci.c1835 pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x11, &reg_val);
1836 bcm_bprintf(b, "MDIO_DEV_TXPLL, pllcontrol: 0x%x\n", reg_val);
1837 pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x12, &reg_val);
1838 bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer1: 0x%x\n", reg_val);
1839 pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x13, &reg_val);
1840 bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer2: 0x%x\n", reg_val);
1841 pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x14, &reg_val);
1842 bcm_bprintf(b, "MDIO_DEV_TXPLL, plltimer3: 0x%x\n", reg_val);
1843 pcie_mdioread(pi, MDIO_DEV_TXPLL, 0x17, &reg_val);
1844 bcm_bprintf(b, "MDIO_DEV_TXPLL, freqdetcounte
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