Searched refs:HCLK (Results 1 - 4 of 4) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-lh7a40x/
H A Dlcd-panel.h65 #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
66 #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
131 #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
132 #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
167 #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
168 #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
200 #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
201 #define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
232 /* Note that with a 99993900 Hz HCLK, it is not possible to hit the
247 #define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/video/
H A Dkyro.h33 u32 HCLK; /* Hor Clock */ member in struct:kyrofb_info
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-lh7a40x/
H A Dconstants.h87 #define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
88 #define HCLK (99993600) macro
89 //#define HCLK (119808000)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/kyro/
H A Dfbdev.c496 par->HCLK = (1000000000 + (lineclock / 2)) / lineclock;

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