1/* lcd-panel.h 2 $Id: lcd-panel.h,v 1.1.1.1 2007/08/03 18:51:37 Exp $ 3 4 written by Marc Singer 5 18 Jul 2005 6 7 Copyright (C) 2005 Marc Singer 8 9 ----------- 10 DESCRIPTION 11 ----------- 12 13 Only one panel may be defined at a time. 14 15 The pixel clock is calculated to be no greater than the target. 16 17 Each timing value is accompanied by a specification comment. 18 19 UNITS/MIN/TYP/MAX 20 21 Most of the units will be in clocks. 22 23 USE_RGB555 24 25 Define this macro to configure the AMBA LCD controller to use an 26 RGB555 encoding for the pels instead of the normal RGB565. 27 28 LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11 29 30 These boards are best approximated by 555 for all panels. Some 31 can use an extra low-order bit of blue in bit 16 of the color 32 value, but we don't have a way to communicate this non-linear 33 mapping to the kernel. 34 35*/ 36 37#if !defined(__LCD_PANEL_H__) 38# define __LCD_PANEL_H__ 39 40#if defined(MACH_LPD79520) || defined(MACH_LPD79524) || defined(MACH_LPD7A400) || \ 41 defined(MACH_LPD7A404) 42# define USE_RGB555 43#endif 44 45struct clcd_panel_extra { 46 unsigned int hrmode; 47 unsigned int clsen; 48 unsigned int spsen; 49 unsigned int pcdel; 50 unsigned int revdel; 51 unsigned int lpdel; 52 unsigned int spldel; 53 unsigned int pc2del; 54}; 55 56#define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000)) 57#define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e)) 58 59#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT 60 61 /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */ 62 /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */ 63 64#define PIX_CLOCK_TARGET (6800000) 65#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 66#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) 67 68static struct clcd_panel lcd_panel = { 69 .mode = { 70 .name = "3.5in QVGA (LQ035Q7DB02)", 71 .xres = 240, 72 .yres = 320, 73 .pixclock = PIX_CLOCK, 74 .left_margin = 16, 75 .right_margin = 21, 76 .upper_margin = 8, // line/8/8/8 77 .lower_margin = 5, 78 .hsync_len = 61, 79 .vsync_len = NS_TO_CLOCK (60, PIX_CLOCK), 80 .vmode = FB_VMODE_NONINTERLACED, 81 }, 82 .width = -1, 83 .height = -1, 84 .tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2), 85 .cntl = CNTL_LCDTFT | CNTL_WATERMARK, 86 .bpp = 16, 87}; 88 89#define HAS_LCD_PANEL_EXTRA 90 91static struct clcd_panel_extra lcd_panel_extra = { 92 .hrmode = 1, 93 .clsen = 1, 94 .spsen = 1, 95 .pcdel = 8, 96 .revdel = 7, 97 .lpdel = 13, 98 .spldel = 77, 99 .pc2del = 208, 100}; 101 102#endif 103 104#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02 105 106 /* Logic Product Development LCD 5.7" QVGA -10 */ 107 /* Sharp PN LQ057Q3DC02 */ 108 /* QVGA mode, V/Q=LOW */ 109 110/* From Sharp on 2006.1.3. I believe some of the values are incorrect 111 * based on the datasheet. 112 113 Timing0 TIMING1 TIMING2 CONTROL 114 0x140A0C4C 0x080504EF 0x013F380D 0x00000829 115 HBP= 20 VBP= 8 BCD= 0 116 HFP= 10 VFP= 5 CPL=319 117 HSW= 12 VSW= 1 IOE= 0 118 PPL= 19 LPP=239 IPC= 1 119 IHS= 1 120 IVS= 1 121 ACB= 0 122 CSEL= 0 123 PCD= 13 124 125 */ 126 127/* The full horizontal cycle (Th) is clock/360/400/450. */ 128/* The full vertical cycle (Tv) is line/251/262/280. */ 129 130#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */ 131#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 132#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) 133 134static struct clcd_panel lcd_panel = { 135 .mode = { 136 .name = "5.7in QVGA (LQ057Q3DC02)", 137 .xres = 320, 138 .yres = 240, 139 .pixclock = PIX_CLOCK, 140 .left_margin = 11, 141 .right_margin = 400-11-320-2, 142 .upper_margin = 7, // line/7/7/7 143 .lower_margin = 262-7-240-2, 144 .hsync_len = 2, // clk/2/96/200 145 .vsync_len = 2, // line/2/-/34 146 .vmode = FB_VMODE_NONINTERLACED, 147 }, 148 .width = -1, 149 .height = -1, 150 .tim2 = TIM2_IHS | TIM2_IVS 151 | (PIX_CLOCK_DIVIDER - 2), 152 .cntl = CNTL_LCDTFT | CNTL_WATERMARK, 153 .bpp = 16, 154}; 155 156#endif 157 158#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343 159 160 /* Logic Product Development LCD 6.4" VGA -10 */ 161 /* Sharp PN LQ64D343 */ 162 163/* The full horizontal cycle (Th) is clock/750/800/900. */ 164/* The full vertical cycle (Tv) is line/515/525/560. */ 165 166#define PIX_CLOCK_TARGET (28330000) 167#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 168#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) 169 170static struct clcd_panel lcd_panel = { 171 .mode = { 172 .name = "6.4in QVGA (LQ64D343)", 173 .xres = 640, 174 .yres = 480, 175 .pixclock = PIX_CLOCK, 176 .left_margin = 32, 177 .right_margin = 800-32-640-96, 178 .upper_margin = 32, // line/34/34/34 179 .lower_margin = 540-32-480-2, 180 .hsync_len = 96, // clk/2/96/200 181 .vsync_len = 2, // line/2/-/34 182 .vmode = FB_VMODE_NONINTERLACED, 183 }, 184 .width = -1, 185 .height = -1, 186 .tim2 = TIM2_IHS | TIM2_IVS 187 | (PIX_CLOCK_DIVIDER - 2), 188 .cntl = CNTL_LCDTFT | CNTL_WATERMARK, 189 .bpp = 16, 190}; 191 192#endif 193 194#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368 195 196 /* Logic Product Development LCD 10.4" VGA -10 */ 197 /* Sharp PN LQ10D368 */ 198 199#define PIX_CLOCK_TARGET (28330000) 200#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 201#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) 202 203static struct clcd_panel lcd_panel = { 204 .mode = { 205 .name = "10.4in VGA (LQ10D368)", 206 .xres = 640, 207 .yres = 480, 208 .pixclock = PIX_CLOCK, 209 .left_margin = 21, 210 .right_margin = 15, 211 .upper_margin = 34, 212 .lower_margin = 5, 213 .hsync_len = 96, 214 .vsync_len = 16, 215 .vmode = FB_VMODE_NONINTERLACED, 216 }, 217 .width = -1, 218 .height = -1, 219 .tim2 = TIM2_IHS | TIM2_IVS 220 | (PIX_CLOCK_DIVIDER - 2), 221 .cntl = CNTL_LCDTFT | CNTL_WATERMARK, 222 .bpp = 16, 223}; 224 225#endif 226 227#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41 228 229 /* Logic Product Development LCD 12.1" SVGA -10 */ 230 /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */ 231 232/* Note that with a 99993900 Hz HCLK, it is not possible to hit the 233 * target clock frequency range of 35MHz to 42MHz. */ 234 235/* If the target pixel clock is substantially lower than the panel 236 * spec, this is done to prevent the LCD display from glitching when 237 * the CPU is under load. A pixel clock higher than 25MHz 238 * (empirically determined) will compete with the CPU for bus cycles 239 * for the Ethernet chip. However, even a pixel clock of 10MHz 240 * competes with Compact Flash interface during some operations 241 * (fdisk, e2fsck). And, at that speed the display may have a visible 242 * flicker. */ 243 244/* The full horizontal cycle (Th) is clock/832/1056/1395. */ 245 246#define PIX_CLOCK_TARGET (20000000) 247#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 248#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) 249 250static struct clcd_panel lcd_panel = { 251 .mode = { 252 .name = "12.1in SVGA (LQ121S1DG41)", 253 .xres = 800, 254 .yres = 600, 255 .pixclock = PIX_CLOCK, 256 .left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10 257 .right_margin = 1056-800-89-128, 258 .upper_margin = 23, // line/23/23/23 259 .lower_margin = 44, 260 .hsync_len = 128, // clk/2/128/200 261 .vsync_len = 4, // line/2/4/6 262 .vmode = FB_VMODE_NONINTERLACED, 263 }, 264 .width = -1, 265 .height = -1, 266 .tim2 = TIM2_IHS | TIM2_IVS 267 | (PIX_CLOCK_DIVIDER - 2), 268 .cntl = CNTL_LCDTFT | CNTL_WATERMARK, 269 .bpp = 16, 270}; 271 272#endif 273 274#if defined CONFIG_FB_ARMCLCD_HITACHI 275 276 /* Hitachi*/ 277 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */ 278 279#define PIX_CLOCK_TARGET (49000000) 280#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 281#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) 282 283static struct clcd_panel lcd_panel = { 284 .mode = { 285 .name = "Hitachi 800x480", 286 .xres = 800, 287 .yres = 480, 288 .pixclock = PIX_CLOCK, 289 .left_margin = 88, 290 .right_margin = 40, 291 .upper_margin = 32, 292 .lower_margin = 11, 293 .hsync_len = 128, 294 .vsync_len = 2, 295 .vmode = FB_VMODE_NONINTERLACED, 296 }, 297 .width = -1, 298 .height = -1, 299 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS 300 | (PIX_CLOCK_DIVIDER - 2), 301 .cntl = CNTL_LCDTFT | CNTL_WATERMARK, 302 .bpp = 16, 303}; 304 305#endif 306 307 308#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE 309 310 /* AU Optotronics A070VW01 7.0 Wide Screen color Display*/ 311 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */ 312 313#define PIX_CLOCK_TARGET (10000000) 314#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK) 315#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER) 316 317static struct clcd_panel lcd_panel = { 318 .mode = { 319 .name = "7.0in Wide (A070VW01)", 320 .xres = 480, 321 .yres = 234, 322 .pixclock = PIX_CLOCK, 323 .left_margin = 30, 324 .right_margin = 25, 325 .upper_margin = 14, 326 .lower_margin = 12, 327 .hsync_len = 100, 328 .vsync_len = 1, 329 .vmode = FB_VMODE_NONINTERLACED, 330 }, 331 .width = -1, 332 .height = -1, 333 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS 334 | (PIX_CLOCK_DIVIDER - 2), 335 .cntl = CNTL_LCDTFT | CNTL_WATERMARK, 336 .bpp = 16, 337}; 338 339#endif 340 341#undef NS_TO_CLOCK 342#undef CLOCK_TO_DIV 343 344#endif /* __LCD_PANEL_H__ */ 345