Searched refs:EBIU_SDRRC (Results 1 - 11 of 11) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S363 p0.l = lo(EBIU_SDRRC);
364 p0.h = hi(EBIU_SDRRC);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S427 p0.l = lo(EBIU_SDRRC);
428 p0.h = hi(EBIU_SDRRC);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S409 p0.l = lo(EBIU_SDRRC);
410 p0.h = hi(EBIU_SDRRC);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A DcdefBF532.h504 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
505 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
H A DdefBF532.h210 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h413 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
414 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
H A DdefBF52x_base.h236 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A DdefBF561.h310 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro
H A DcdefBF561.h547 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
548 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h396 #define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
397 #define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC,val)
H A DdefBF534.h215 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ macro

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