Searched refs:EBIU_AMBCTL1 (Results 1 - 13 of 13) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S172 p2.h = hi(EBIU_AMBCTL1);
173 p2.l = lo(EBIU_AMBCTL1);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S226 p2.h = hi(EBIU_AMBCTL1);
227 p2.l = lo(EBIU_AMBCTL1);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S217 p2.h = hi(EBIU_AMBCTL1);
218 p2.l = lo(EBIU_AMBCTL1);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A DcdefBF532.h498 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
499 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
H A DdefBF532.h204 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DcdefBF52x_base.h407 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
408 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
H A DdefBF52x_base.h233 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
1247 /* EBIU_AMBCTL1 Masks */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A DdefBF561.h305 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
H A DcdefBF561.h540 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
541 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A DcdefBF534.h390 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
391 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1,val)
H A DdefBF534.h212 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ macro
1507 /* EBIU_AMBCTL1 Masks */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-blackfin/mach-bf548/
H A DdefBF54x_base.h172 #define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */ macro
1788 /* Bit masks for EBIU_AMBCTL1 */
4892 #define EBIU_AMCBCTL1 EBIU_AMBCTL1
H A DcdefBF54x_base.h270 #define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
271 #define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)

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