Searched refs:ARM_CKCTL (Results 1 - 5 of 5) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/plat-omap/
H A Dsram-fn.S28 mov r3, #IO_ADDRESS(ARM_CKCTL) & 0xff000000
29 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
30 orr r3, r3, #IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-omap1/
H A Dclock.c215 dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
568 regval = omap_readw(ARM_CKCTL);
572 omap_writew(regval, ARM_CKCTL);
703 printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
705 omap_readw(ARM_CKCTL));
744 omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
771 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
773 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); local
[all...]
H A Dpm.c241 #define EN_DSPCK 13 /* ARM_CKCTL */
307 ARM_SAVE(ARM_CKCTL);
330 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
398 ARM_RESTORE(ARM_CKCTL);
471 ARM_SAVE(ARM_CKCTL);
529 ARM_SHOW(ARM_CKCTL),
H A Dclock.h56 /* ARM_CKCTL bit shifts */
274 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
287 .enable_reg = (void __iomem *)ARM_CKCTL,
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-omap/
H A Dhardware.h74 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro

Completed in 101 milliseconds