1/* 2 * linux/arch/arm/mach-omap1/pm.c 3 * 4 * OMAP Power Management Routines 5 * 6 * Original code for the SA11x0: 7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com> 8 * 9 * Modified for the PXA250 by Nicolas Pitre: 10 * Copyright (c) 2002 Monta Vista Software, Inc. 11 * 12 * Modified for the OMAP1510 by David Singleton: 13 * Copyright (c) 2002 Monta Vista Software, Inc. 14 * 15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com> 16 * 17 * This program is free software; you can redistribute it and/or modify it 18 * under the terms of the GNU General Public License as published by the 19 * Free Software Foundation; either version 2 of the License, or (at your 20 * option) any later version. 21 * 22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * You should have received a copy of the GNU General Public License along 34 * with this program; if not, write to the Free Software Foundation, Inc., 35 * 675 Mass Ave, Cambridge, MA 02139, USA. 36 */ 37 38#include <linux/pm.h> 39#include <linux/sched.h> 40#include <linux/proc_fs.h> 41#include <linux/pm.h> 42#include <linux/interrupt.h> 43#include <linux/sysfs.h> 44#include <linux/module.h> 45 46#include <asm/io.h> 47#include <asm/irq.h> 48#include <asm/atomic.h> 49#include <asm/mach/time.h> 50#include <asm/mach/irq.h> 51#include <asm/mach-types.h> 52 53#include <asm/arch/cpu.h> 54#include <asm/arch/irqs.h> 55#include <asm/arch/clock.h> 56#include <asm/arch/sram.h> 57#include <asm/arch/tc.h> 58#include <asm/arch/pm.h> 59#include <asm/arch/mux.h> 60#include <asm/arch/tps65010.h> 61#include <asm/arch/dma.h> 62#include <asm/arch/dsp_common.h> 63#include <asm/arch/dmtimer.h> 64 65static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 66static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; 67static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; 68static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE]; 69static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; 70static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; 71 72static unsigned short enable_dyn_sleep = 1; 73 74static ssize_t omap_pm_sleep_while_idle_show(struct kset *kset, char *buf) 75{ 76 return sprintf(buf, "%hu\n", enable_dyn_sleep); 77} 78 79static ssize_t omap_pm_sleep_while_idle_store(struct kset *kset, 80 const char * buf, 81 size_t n) 82{ 83 unsigned short value; 84 if (sscanf(buf, "%hu", &value) != 1 || 85 (value != 0 && value != 1)) { 86 printk(KERN_ERR "idle_sleep_store: Invalid value\n"); 87 return -EINVAL; 88 } 89 enable_dyn_sleep = value; 90 return n; 91} 92 93static struct subsys_attribute sleep_while_idle_attr = { 94 .attr = { 95 .name = __stringify(sleep_while_idle), 96 .mode = 0644, 97 }, 98 .show = omap_pm_sleep_while_idle_show, 99 .store = omap_pm_sleep_while_idle_store, 100}; 101 102extern struct kset power_subsys; 103static void (*omap_sram_idle)(void) = NULL; 104static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; 105 106/* 107 * Let's power down on idle, but only if we are really 108 * idle, because once we start down the path of 109 * going idle we continue to do idle even if we get 110 * a clock tick interrupt . . 111 */ 112void omap_pm_idle(void) 113{ 114 extern __u32 arm_idlect1_mask; 115 __u32 use_idlect1 = arm_idlect1_mask; 116#ifndef CONFIG_OMAP_MPU_TIMER 117 int do_sleep; 118#endif 119 120 local_irq_disable(); 121 local_fiq_disable(); 122 if (need_resched()) { 123 local_fiq_enable(); 124 local_irq_enable(); 125 return; 126 } 127 128 /* 129 * Since an interrupt may set up a timer, we don't want to 130 * reprogram the hardware timer with interrupts enabled. 131 * Re-enable interrupts only after returning from idle. 132 */ 133 timer_dyn_reprogram(); 134 135#ifdef CONFIG_OMAP_MPU_TIMER 136#warning Enable 32kHz OS timer in order to allow sleep states in idle 137 use_idlect1 = use_idlect1 & ~(1 << 9); 138#else 139 140 do_sleep = 0; 141 while (enable_dyn_sleep) { 142 143#ifdef CONFIG_CBUS_TAHVO_USB 144 extern int vbus_active; 145 /* Clock requirements? */ 146 if (vbus_active) 147 break; 148#endif 149 do_sleep = 1; 150 break; 151 } 152 153#ifdef CONFIG_OMAP_DM_TIMER 154 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); 155#endif 156 157 if (omap_dma_running()) { 158 use_idlect1 &= ~(1 << 6); 159 if (omap_lcd_dma_ext_running()) 160 use_idlect1 &= ~(1 << 12); 161 } 162 163 /* We should be able to remove the do_sleep variable and multiple 164 * tests above as soon as drivers, timer and DMA code have been fixed. 165 * Even the sleep block count should become obsolete. */ 166 if ((use_idlect1 != ~0) || !do_sleep) { 167 168 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1); 169 if (cpu_is_omap15xx()) 170 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST; 171 else 172 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL; 173 omap_writel(use_idlect1, ARM_IDLECT1); 174 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); 175 omap_writel(saved_idlect1, ARM_IDLECT1); 176 177 local_fiq_enable(); 178 local_irq_enable(); 179 return; 180 } 181 omap_sram_suspend(omap_readl(ARM_IDLECT1), 182 omap_readl(ARM_IDLECT2)); 183#endif 184 185 local_fiq_enable(); 186 local_irq_enable(); 187} 188 189/* 190 * Configuration of the wakeup event is board specific. For the 191 * moment we put it into this helper function. Later it may move 192 * to board specific files. 193 */ 194static void omap_pm_wakeup_setup(void) 195{ 196 u32 level1_wake = 0; 197 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2); 198 199 /* 200 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, 201 * and the L2 wakeup interrupts: keypad and UART2. Note that the 202 * drivers must still separately call omap_set_gpio_wakeup() to 203 * wake up to a GPIO interrupt. 204 */ 205 if (cpu_is_omap730()) 206 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) | 207 OMAP_IRQ_BIT(INT_730_IH2_IRQ); 208 else if (cpu_is_omap15xx()) 209 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 210 OMAP_IRQ_BIT(INT_1510_IH2_IRQ); 211 else if (cpu_is_omap16xx()) 212 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | 213 OMAP_IRQ_BIT(INT_1610_IH2_IRQ); 214 215 omap_writel(~level1_wake, OMAP_IH1_MIR); 216 217 if (cpu_is_omap730()) { 218 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 219 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) | 220 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)), 221 OMAP_IH2_1_MIR); 222 } else if (cpu_is_omap15xx()) { 223 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 224 omap_writel(~level2_wake, OMAP_IH2_MIR); 225 } else if (cpu_is_omap16xx()) { 226 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); 227 omap_writel(~level2_wake, OMAP_IH2_0_MIR); 228 229 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ 230 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), 231 OMAP_IH2_1_MIR); 232 omap_writel(~0x0, OMAP_IH2_2_MIR); 233 omap_writel(~0x0, OMAP_IH2_3_MIR); 234 } 235 236 /* New IRQ agreement, recalculate in cascade order */ 237 omap_writel(1, OMAP_IH2_CONTROL); 238 omap_writel(1, OMAP_IH1_CONTROL); 239} 240 241#define EN_DSPCK 13 /* ARM_CKCTL */ 242#define EN_APICK 6 /* ARM_IDLECT2 */ 243#define DSP_EN 1 /* ARM_RSTCT1 */ 244 245void omap_pm_suspend(void) 246{ 247 unsigned long arg0 = 0, arg1 = 0; 248 249 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev); 250 251 omap_serial_wake_trigger(1); 252 253 if (machine_is_omap_osk()) { 254 /* Stop LED1 (D9) blink */ 255 tps65010_set_led(LED1, OFF); 256 } 257 258 if (!cpu_is_omap15xx()) 259 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG); 260 261 262 local_irq_disable(); 263 local_fiq_disable(); 264 265 /* 266 * Step 2: save registers 267 * 268 * The omap is a strange/beautiful device. The caches, memory 269 * and register state are preserved across power saves. 270 * We have to save and restore very little register state to 271 * idle the omap. 272 * 273 * Save interrupt, MPUI, ARM and UPLD control registers. 274 */ 275 276 if (cpu_is_omap730()) { 277 MPUI730_SAVE(OMAP_IH1_MIR); 278 MPUI730_SAVE(OMAP_IH2_0_MIR); 279 MPUI730_SAVE(OMAP_IH2_1_MIR); 280 MPUI730_SAVE(MPUI_CTRL); 281 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 282 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 283 MPUI730_SAVE(EMIFS_CONFIG); 284 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 285 286 } else if (cpu_is_omap15xx()) { 287 MPUI1510_SAVE(OMAP_IH1_MIR); 288 MPUI1510_SAVE(OMAP_IH2_MIR); 289 MPUI1510_SAVE(MPUI_CTRL); 290 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 291 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 292 MPUI1510_SAVE(EMIFS_CONFIG); 293 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 294 } else if (cpu_is_omap16xx()) { 295 MPUI1610_SAVE(OMAP_IH1_MIR); 296 MPUI1610_SAVE(OMAP_IH2_0_MIR); 297 MPUI1610_SAVE(OMAP_IH2_1_MIR); 298 MPUI1610_SAVE(OMAP_IH2_2_MIR); 299 MPUI1610_SAVE(OMAP_IH2_3_MIR); 300 MPUI1610_SAVE(MPUI_CTRL); 301 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 302 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 303 MPUI1610_SAVE(EMIFS_CONFIG); 304 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 305 } 306 307 ARM_SAVE(ARM_CKCTL); 308 ARM_SAVE(ARM_IDLECT1); 309 ARM_SAVE(ARM_IDLECT2); 310 if (!(cpu_is_omap15xx())) 311 ARM_SAVE(ARM_IDLECT3); 312 ARM_SAVE(ARM_EWUPCT); 313 ARM_SAVE(ARM_RSTCT1); 314 ARM_SAVE(ARM_RSTCT2); 315 ARM_SAVE(ARM_SYSST); 316 ULPD_SAVE(ULPD_CLOCK_CTRL); 317 ULPD_SAVE(ULPD_STATUS_REQ); 318 319 /* (Step 3 removed - we now allow deep sleep by default) */ 320 321 /* 322 * Step 4: OMAP DSP Shutdown 323 */ 324 325 /* stop DSP */ 326 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); 327 328 /* shut down dsp_ck */ 329 if (!cpu_is_omap730()) 330 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); 331 332 /* temporarily enabling api_ck to access DSP registers */ 333 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 334 335 /* save DSP registers */ 336 DSP_SAVE(DSP_IDLECT2); 337 338 /* Stop all DSP domain clocks */ 339 __raw_writew(0, DSP_IDLECT2); 340 341 /* 342 * Step 5: Wakeup Event Setup 343 */ 344 345 omap_pm_wakeup_setup(); 346 347 /* 348 * Step 6: ARM and Traffic controller shutdown 349 */ 350 351 /* disable ARM watchdog */ 352 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE); 353 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE); 354 355 /* 356 * Step 6b: ARM and Traffic controller shutdown 357 * 358 * Step 6 continues here. Prepare jump to power management 359 * assembly code in internal SRAM. 360 * 361 * Since the omap_cpu_suspend routine has been copied to 362 * SRAM, we'll do an indirect procedure call to it and pass the 363 * contents of arm_idlect1 and arm_idlect2 so it can restore 364 * them when it wakes up and it will return. 365 */ 366 367 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; 368 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; 369 370 /* 371 * Step 6c: ARM and Traffic controller shutdown 372 * 373 * Jump to assembly code. The processor will stay there 374 * until wake up. 375 */ 376 omap_sram_suspend(arg0, arg1); 377 378 /* 379 * If we are here, processor is woken up! 380 */ 381 382 /* 383 * Restore DSP clocks 384 */ 385 386 /* again temporarily enabling api_ck to access DSP registers */ 387 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); 388 389 /* Restore DSP domain clocks */ 390 DSP_RESTORE(DSP_IDLECT2); 391 392 /* 393 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did 394 */ 395 396 if (!(cpu_is_omap15xx())) 397 ARM_RESTORE(ARM_IDLECT3); 398 ARM_RESTORE(ARM_CKCTL); 399 ARM_RESTORE(ARM_EWUPCT); 400 ARM_RESTORE(ARM_RSTCT1); 401 ARM_RESTORE(ARM_RSTCT2); 402 ARM_RESTORE(ARM_SYSST); 403 ULPD_RESTORE(ULPD_CLOCK_CTRL); 404 ULPD_RESTORE(ULPD_STATUS_REQ); 405 406 if (cpu_is_omap730()) { 407 MPUI730_RESTORE(EMIFS_CONFIG); 408 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG); 409 MPUI730_RESTORE(OMAP_IH1_MIR); 410 MPUI730_RESTORE(OMAP_IH2_0_MIR); 411 MPUI730_RESTORE(OMAP_IH2_1_MIR); 412 } else if (cpu_is_omap15xx()) { 413 MPUI1510_RESTORE(MPUI_CTRL); 414 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); 415 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); 416 MPUI1510_RESTORE(EMIFS_CONFIG); 417 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG); 418 MPUI1510_RESTORE(OMAP_IH1_MIR); 419 MPUI1510_RESTORE(OMAP_IH2_MIR); 420 } else if (cpu_is_omap16xx()) { 421 MPUI1610_RESTORE(MPUI_CTRL); 422 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG); 423 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG); 424 MPUI1610_RESTORE(EMIFS_CONFIG); 425 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG); 426 427 MPUI1610_RESTORE(OMAP_IH1_MIR); 428 MPUI1610_RESTORE(OMAP_IH2_0_MIR); 429 MPUI1610_RESTORE(OMAP_IH2_1_MIR); 430 MPUI1610_RESTORE(OMAP_IH2_2_MIR); 431 MPUI1610_RESTORE(OMAP_IH2_3_MIR); 432 } 433 434 if (!cpu_is_omap15xx()) 435 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); 436 437 /* 438 * Re-enable interrupts 439 */ 440 441 local_irq_enable(); 442 local_fiq_enable(); 443 444 omap_serial_wake_trigger(0); 445 446 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev); 447 448 if (machine_is_omap_osk()) { 449 /* Let LED1 (D9) blink again */ 450 tps65010_set_led(LED1, BLINK); 451 } 452} 453 454#if defined(DEBUG) && defined(CONFIG_PROC_FS) 455static int g_read_completed; 456 457/* 458 * Read system PM registers for debugging 459 */ 460static int omap_pm_read_proc( 461 char *page_buffer, 462 char **my_first_byte, 463 off_t virtual_start, 464 int length, 465 int *eof, 466 void *data) 467{ 468 int my_buffer_offset = 0; 469 char * const my_base = page_buffer; 470 471 ARM_SAVE(ARM_CKCTL); 472 ARM_SAVE(ARM_IDLECT1); 473 ARM_SAVE(ARM_IDLECT2); 474 if (!(cpu_is_omap15xx())) 475 ARM_SAVE(ARM_IDLECT3); 476 ARM_SAVE(ARM_EWUPCT); 477 ARM_SAVE(ARM_RSTCT1); 478 ARM_SAVE(ARM_RSTCT2); 479 ARM_SAVE(ARM_SYSST); 480 481 ULPD_SAVE(ULPD_IT_STATUS); 482 ULPD_SAVE(ULPD_CLOCK_CTRL); 483 ULPD_SAVE(ULPD_SOFT_REQ); 484 ULPD_SAVE(ULPD_STATUS_REQ); 485 ULPD_SAVE(ULPD_DPLL_CTRL); 486 ULPD_SAVE(ULPD_POWER_CTRL); 487 488 if (cpu_is_omap730()) { 489 MPUI730_SAVE(MPUI_CTRL); 490 MPUI730_SAVE(MPUI_DSP_STATUS); 491 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG); 492 MPUI730_SAVE(MPUI_DSP_API_CONFIG); 493 MPUI730_SAVE(EMIFF_SDRAM_CONFIG); 494 MPUI730_SAVE(EMIFS_CONFIG); 495 } else if (cpu_is_omap15xx()) { 496 MPUI1510_SAVE(MPUI_CTRL); 497 MPUI1510_SAVE(MPUI_DSP_STATUS); 498 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); 499 MPUI1510_SAVE(MPUI_DSP_API_CONFIG); 500 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); 501 MPUI1510_SAVE(EMIFS_CONFIG); 502 } else if (cpu_is_omap16xx()) { 503 MPUI1610_SAVE(MPUI_CTRL); 504 MPUI1610_SAVE(MPUI_DSP_STATUS); 505 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); 506 MPUI1610_SAVE(MPUI_DSP_API_CONFIG); 507 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); 508 MPUI1610_SAVE(EMIFS_CONFIG); 509 } 510 511 if (virtual_start == 0) { 512 g_read_completed = 0; 513 514 my_buffer_offset += sprintf(my_base + my_buffer_offset, 515 "ARM_CKCTL_REG: 0x%-8x \n" 516 "ARM_IDLECT1_REG: 0x%-8x \n" 517 "ARM_IDLECT2_REG: 0x%-8x \n" 518 "ARM_IDLECT3_REG: 0x%-8x \n" 519 "ARM_EWUPCT_REG: 0x%-8x \n" 520 "ARM_RSTCT1_REG: 0x%-8x \n" 521 "ARM_RSTCT2_REG: 0x%-8x \n" 522 "ARM_SYSST_REG: 0x%-8x \n" 523 "ULPD_IT_STATUS_REG: 0x%-4x \n" 524 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n" 525 "ULPD_SOFT_REQ_REG: 0x%-4x \n" 526 "ULPD_DPLL_CTRL_REG: 0x%-4x \n" 527 "ULPD_STATUS_REQ_REG: 0x%-4x \n" 528 "ULPD_POWER_CTRL_REG: 0x%-4x \n", 529 ARM_SHOW(ARM_CKCTL), 530 ARM_SHOW(ARM_IDLECT1), 531 ARM_SHOW(ARM_IDLECT2), 532 ARM_SHOW(ARM_IDLECT3), 533 ARM_SHOW(ARM_EWUPCT), 534 ARM_SHOW(ARM_RSTCT1), 535 ARM_SHOW(ARM_RSTCT2), 536 ARM_SHOW(ARM_SYSST), 537 ULPD_SHOW(ULPD_IT_STATUS), 538 ULPD_SHOW(ULPD_CLOCK_CTRL), 539 ULPD_SHOW(ULPD_SOFT_REQ), 540 ULPD_SHOW(ULPD_DPLL_CTRL), 541 ULPD_SHOW(ULPD_STATUS_REQ), 542 ULPD_SHOW(ULPD_POWER_CTRL)); 543 544 if (cpu_is_omap730()) { 545 my_buffer_offset += sprintf(my_base + my_buffer_offset, 546 "MPUI730_CTRL_REG 0x%-8x \n" 547 "MPUI730_DSP_STATUS_REG: 0x%-8x \n" 548 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 549 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n" 550 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n" 551 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n", 552 MPUI730_SHOW(MPUI_CTRL), 553 MPUI730_SHOW(MPUI_DSP_STATUS), 554 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG), 555 MPUI730_SHOW(MPUI_DSP_API_CONFIG), 556 MPUI730_SHOW(EMIFF_SDRAM_CONFIG), 557 MPUI730_SHOW(EMIFS_CONFIG)); 558 } else if (cpu_is_omap15xx()) { 559 my_buffer_offset += sprintf(my_base + my_buffer_offset, 560 "MPUI1510_CTRL_REG 0x%-8x \n" 561 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n" 562 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 563 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n" 564 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n" 565 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n", 566 MPUI1510_SHOW(MPUI_CTRL), 567 MPUI1510_SHOW(MPUI_DSP_STATUS), 568 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG), 569 MPUI1510_SHOW(MPUI_DSP_API_CONFIG), 570 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG), 571 MPUI1510_SHOW(EMIFS_CONFIG)); 572 } else if (cpu_is_omap16xx()) { 573 my_buffer_offset += sprintf(my_base + my_buffer_offset, 574 "MPUI1610_CTRL_REG 0x%-8x \n" 575 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n" 576 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n" 577 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n" 578 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n" 579 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n", 580 MPUI1610_SHOW(MPUI_CTRL), 581 MPUI1610_SHOW(MPUI_DSP_STATUS), 582 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG), 583 MPUI1610_SHOW(MPUI_DSP_API_CONFIG), 584 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG), 585 MPUI1610_SHOW(EMIFS_CONFIG)); 586 } 587 588 g_read_completed++; 589 } else if (g_read_completed >= 1) { 590 *eof = 1; 591 return 0; 592 } 593 g_read_completed++; 594 595 *my_first_byte = page_buffer; 596 return my_buffer_offset; 597} 598 599static void omap_pm_init_proc(void) 600{ 601 struct proc_dir_entry *entry; 602 603 entry = create_proc_read_entry("driver/omap_pm", 604 S_IWUSR | S_IRUGO, NULL, 605 omap_pm_read_proc, NULL); 606} 607 608#endif /* DEBUG && CONFIG_PROC_FS */ 609 610static void (*saved_idle)(void) = NULL; 611 612/* 613 * omap_pm_prepare - Do preliminary suspend work. 614 * @state: suspend state we're entering. 615 * 616 */ 617static int omap_pm_prepare(suspend_state_t state) 618{ 619 int error = 0; 620 621 /* We cannot sleep in idle until we have resumed */ 622 saved_idle = pm_idle; 623 pm_idle = NULL; 624 625 switch (state) 626 { 627 case PM_SUSPEND_STANDBY: 628 case PM_SUSPEND_MEM: 629 break; 630 default: 631 return -EINVAL; 632 } 633 634 return error; 635} 636 637 638/* 639 * omap_pm_enter - Actually enter a sleep state. 640 * @state: State we're entering. 641 * 642 */ 643 644static int omap_pm_enter(suspend_state_t state) 645{ 646 switch (state) 647 { 648 case PM_SUSPEND_STANDBY: 649 case PM_SUSPEND_MEM: 650 omap_pm_suspend(); 651 break; 652 default: 653 return -EINVAL; 654 } 655 656 return 0; 657} 658 659 660/** 661 * omap_pm_finish - Finish up suspend sequence. 662 * @state: State we're coming out of. 663 * 664 * This is called after we wake back up (or if entering the sleep state 665 * failed). 666 */ 667 668static int omap_pm_finish(suspend_state_t state) 669{ 670 pm_idle = saved_idle; 671 return 0; 672} 673 674 675static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) 676{ 677 return IRQ_HANDLED; 678} 679 680static struct irqaction omap_wakeup_irq = { 681 .name = "peripheral wakeup", 682 .flags = IRQF_DISABLED, 683 .handler = omap_wakeup_interrupt 684}; 685 686 687 688static struct pm_ops omap_pm_ops ={ 689 .prepare = omap_pm_prepare, 690 .enter = omap_pm_enter, 691 .finish = omap_pm_finish, 692 .valid = pm_valid_only_mem, 693}; 694 695static int __init omap_pm_init(void) 696{ 697 int error; 698 699 printk("Power Management for TI OMAP.\n"); 700 701 /* 702 * We copy the assembler sleep/wakeup routines to SRAM. 703 * These routines need to be in SRAM as that's the only 704 * memory the MPU can see when it wakes up. 705 */ 706 if (cpu_is_omap730()) { 707 omap_sram_idle = omap_sram_push(omap730_idle_loop_suspend, 708 omap730_idle_loop_suspend_sz); 709 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend, 710 omap730_cpu_suspend_sz); 711 } else if (cpu_is_omap15xx()) { 712 omap_sram_idle = omap_sram_push(omap1510_idle_loop_suspend, 713 omap1510_idle_loop_suspend_sz); 714 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, 715 omap1510_cpu_suspend_sz); 716 } else if (cpu_is_omap16xx()) { 717 omap_sram_idle = omap_sram_push(omap1610_idle_loop_suspend, 718 omap1610_idle_loop_suspend_sz); 719 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, 720 omap1610_cpu_suspend_sz); 721 } 722 723 if (omap_sram_idle == NULL || omap_sram_suspend == NULL) { 724 printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); 725 return -ENODEV; 726 } 727 728 pm_idle = omap_pm_idle; 729 730 if (cpu_is_omap730()) 731 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq); 732 else if (cpu_is_omap16xx()) 733 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq); 734 735 /* Program new power ramp-up time 736 * (0 for most boards since we don't lower voltage when in deep sleep) 737 */ 738 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); 739 740 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ 741 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); 742 743 /* Configure IDLECT3 */ 744 if (cpu_is_omap730()) 745 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3); 746 else if (cpu_is_omap16xx()) 747 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); 748 749 pm_set_ops(&omap_pm_ops); 750 751#if defined(DEBUG) && defined(CONFIG_PROC_FS) 752 omap_pm_init_proc(); 753#endif 754 755 error = subsys_create_file(&power_subsys, &sleep_while_idle_attr); 756 if (error) 757 printk(KERN_ERR "subsys_create_file failed: %d\n", error); 758 759 if (cpu_is_omap16xx()) { 760 /* configure LOW_PWR pin */ 761 omap_cfg_reg(T20_1610_LOW_PWR); 762 } 763 764 return 0; 765} 766__initcall(omap_pm_init); 767