Searched refs:rate (Results 1 - 25 of 449) sorted by relevance

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/netgear-WNDR4500-V1.0.1.40_1.0.68/ap/gpl/minidlna/libvorbis-1.2.3/lib/
H A Dbarkmel.c22 double rate; local
24 rate=48000.f;
25 fprintf(stderr,"rate=%gHz, block=%d, f(1)=%.2gHz bark(1)=%.2g (of %.2g)\n",
26 rate,i,rate/2 / (i/2),toBARK(rate/2 /(i/2)),toBARK(rate/2));
28 rate=44100.f;
29 fprintf(stderr,"rate=%gHz, block=%d, f(1)=%.2gHz bark(1)=%.2g (of %.2g)\n",
30 rate,
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/netgear-WNDR4500-V1.0.1.40_1.0.68/ap/gpl/iproute2/tc/
H A Dtc_cbq.h4 unsigned tc_cbq_calc_maxidle(unsigned bndw, unsigned rate, unsigned avpkt,
6 unsigned tc_cbq_calc_offtime(unsigned bndw, unsigned rate, unsigned avpkt,
H A Dq_tbf.c28 fprintf(stderr, "Usage: ... tbf limit BYTES burst BYTES[/BYTES] rate KBPS [ mtu BYTES[/BYTES] ]\n");
111 } else if (strcmp(*argv, "rate") == 0) {
113 if (opt.rate.rate) {
114 fprintf(stderr, "Double \"rate\" spec\n");
117 if (get_rate(&opt.rate.rate, *argv)) {
118 explain1("rate");
124 if (opt.peakrate.rate) {
128 if (get_rate(&opt.peakrate.rate, *arg
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H A Dm_police.c37 fprintf(stderr, "Usage: ... police rate BPS burst BYTES[/BYTES] [ mtu BYTES[/BYTES] ]\n");
191 } else if (strcmp(*argv, "rate") == 0) {
193 if (p.rate.rate) {
194 fprintf(stderr, "Double \"rate\" spec\n");
197 if (get_rate(&p.rate.rate, *argv)) {
198 explain1("rate");
213 if (p.peakrate.rate) {
217 if (get_rate(&p.peakrate.rate, *arg
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/v850/kernel/
H A Dv850e_utils.c29 unsigned long rate,
39 /* Minimum interrupt rate possible using this divider. */
43 if (min_int_rate <= rate) {
59 *count = ((base_freq >> _divlog2) + rate/2) / rate;
28 calc_counter_params(unsigned long base_freq, unsigned long rate, unsigned min_divlog2, unsigned max_divlog2, unsigned counter_size, unsigned *divlog2, unsigned *count) argument
H A Dv850e_timer_d.c23 void v850e_timer_d_configure (unsigned timer, unsigned rate) argument
29 V850E_TIMER_D_BASE_FREQ, rate,
34 " for rate of %dHz.\n"
35 "Using rate of %dHz instead.\n",
36 timer, rate,
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-v850/
H A Dv850e_utils.h30 unsigned long rate,
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-ep93xx/
H A Dclock.c24 unsigned long rate; member in struct:clk
32 .rate = 14745600,
102 return clk->rate;
116 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
120 unsigned long long rate; local
123 rate = 14745600;
124 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
125 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
126 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
128 rate >>
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c27 clk->rate = clk->parent->rate / frqcr3_divisors[idx];
30 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) argument
32 int divisor = clk->parent->rate / rate;
56 clk->rate = clk->parent->rate / frqcr3_divisors[idx];
80 * that passes rate verification..
85 if (clk->ops->set_rate(clk, clk->parent->rate /
96 clk->rate
99 shoc_clk_verify_rate(struct clk *clk, unsigned long rate) argument
114 shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id) argument
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H A Dclock-sh4.c31 clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007];
41 clk->rate = clk->parent->rate / pfc_divisors[idx];
51 clk->rate = clk->parent->rate / bfc_divisors[idx];
61 clk->rate = clk->parent->rate / ifc_divisors[idx];
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7785.c29 clk->rate *= 36;
39 clk->rate = clk->parent->rate / pfc_divisors[idx];
49 clk->rate = clk->parent->rate / bfc_divisors[idx];
59 clk->rate = clk->parent->rate / ifc_divisors[idx];
82 clk->rate = clk->parent->rate / sfc_divisors[idx];
98 clk->rate
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H A Dclock-sh73180.c32 clk->rate *= divisors[ctrl_inl(FRQCR) & 0x0007];
42 clk->rate = clk->parent->rate / divisors[idx];
52 clk->rate = clk->parent->rate / divisors[idx];
62 clk->rate = clk->parent->rate / divisors[idx];
H A Dclock-sh7770.c24 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f];
34 clk->rate = clk->parent->rate / pfc_divisors[idx];
44 clk->rate = clk->parent->rate / bfc_divisors[idx];
54 clk->rate = clk->parent->rate / ifc_divisors[idx];
H A Dclock-sh7780.c25 clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003];
35 clk->rate = clk->parent->rate / pfc_divisors[idx];
45 clk->rate = clk->parent->rate / bfc_divisors[idx];
55 clk->rate = clk->parent->rate / ifc_divisors[idx];
78 clk->rate = clk->parent->rate / cfc_divisors[idx];
115 * automatically figure out their rate
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-omap1/
H A Dclock.c40 clk->rate = clk->parent->rate / 14;
47 clk->rate = 48000000;
49 clk->rate = 12000000;
175 static int calc_dsor_exp(struct clk *clk, unsigned long rate) argument
199 realrate = parent->rate;
201 if (realrate <= rate)
217 if (unlikely(clk->rate == clk->parent->rate / dsor))
219 clk->rate
249 omap1_select_table_rate(struct clk * clk, unsigned long rate) argument
288 omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) argument
315 omap1_round_to_table_rate(struct clk * clk, unsigned long rate) argument
340 calc_ext_dsor(unsigned long rate) argument
363 omap1_set_uart_rate(struct clk * clk, unsigned long rate) argument
381 omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) argument
399 omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) argument
531 omap1_clk_round_rate(struct clk *clk, unsigned long rate) argument
553 omap1_clk_set_rate(struct clk *clk, unsigned long rate) argument
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/sh/kernel/cpu/sh2/
H A Dclock-sh7619.c34 clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
44 clk->rate = clk->parent->rate / pfc_divisors[idx];
53 clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
62 clk->rate = clk->parent->rate;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7206.c37 clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
47 clk->rate = clk->parent->rate / pfc_divisors[idx];
56 clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
66 clk->rate = clk->parent->rate / ifc_divisors[idx];
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/sh/kernel/cpu/sh3/
H A Dclock-sh3.c34 clk->rate *= pfc_divisors[idx];
46 clk->rate = clk->parent->rate / pfc_divisors[idx];
58 clk->rate = clk->parent->rate / stc_multipliers[idx];
70 clk->rate = clk->parent->rate / ifc_divisors[idx];
H A Dclock-sh7300.c29 clk->rate *= md_table[ctrl_inw(FRQCR) & 0x0007];
39 clk->rate = clk->parent->rate / md_table[idx];
49 clk->rate = clk->parent->rate / md_table[idx];
59 clk->rate = clk->parent->rate / md_table[idx];
H A Dclock-sh7705.c35 clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0003];
45 clk->rate = clk->parent->rate / pfc_divisors[idx];
55 clk->rate = clk->parent->rate / stc_multipliers[idx];
65 clk->rate = clk->parent->rate / ifc_divisors[idx];
H A Dclock-sh7706.c30 clk->rate *= pfc_divisors[idx];
42 clk->rate = clk->parent->rate / pfc_divisors[idx];
54 clk->rate = clk->parent->rate / stc_multipliers[idx];
66 clk->rate = clk->parent->rate / ifc_divisors[idx];
/netgear-WNDR4500-V1.0.1.40_1.0.68/ap/gpl/minidlna/libvorbis-1.2.3/include/vorbis/
H A Dvorbisenc.h30 long rate,
38 long rate,
46 long rate,
53 long rate,
62 /* deprecated rate management supported only for compatability */
82 /* new rate setup */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-aaec2000/
H A Dclock.h16 unsigned long rate; member in struct:clk
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/linux/
H A Dclk.h66 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
89 * clk_round_rate - adjust a rate to the exact rate a clock can provide
91 * @rate: desired clock rate in Hz
93 * Returns rounded clock rate in Hz, or negative errno.
95 long clk_round_rate(struct clk *clk, unsigned long rate);
98 * clk_set_rate - set the clock rate for a clock source
100 * @rate: desired clock rate i
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-pnx4008/
H A Dclock.c37 static int local_set_rate(struct clk *clk, u32 rate);
111 if (!clk->rate)
130 if (!clk->rate)
144 if (!clk->rate)
163 if (!clk->rate)
186 * Possible input: up to 320MHz with step of clk->parent->rate.
187 * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
189 * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
190 * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
194 static int pll160_set_rate(struct clk *clk, u32 rate) argument
283 per_clk_set_rate(struct clk *clk, u32 rate) argument
296 hclk_set_rate(struct clk *clk, u32 rate) argument
317 hclk_round_rate(struct clk *clk, u32 rate) argument
327 per_clk_round_rate(struct clk *clk, u32 rate) argument
332 on_off_set_rate(struct clk *clk, u32 rate) argument
344 on_off_inv_set_rate(struct clk *clk, u32 rate) argument
356 on_off_round_rate(struct clk *clk, u32 rate) argument
361 pll4_round_rate(struct clk *clk, u32 rate) argument
370 pll3_round_rate(struct clk *clk, u32 rate) argument
377 pll5_round_rate(struct clk *clk, u32 rate) argument
382 ck_13MHz_round_rate(struct clk *clk, u32 rate) argument
387 ck_13MHz_set_rate(struct clk *clk, u32 rate) argument
402 pll1_set_rate(struct clk *clk, u32 rate) argument
814 local_set_rate(struct clk *clk, u32 rate) argument
830 clk_set_rate(struct clk *clk, unsigned long rate) argument
915 clk_round_rate(struct clk *clk, unsigned long rate) argument
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