Searched refs:SI_CORE_SIZE (Results 1 - 8 of 8) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/shared/
H A Daiutils.c132 cpu = REG_MAP(sii->wrapba[3], SI_CORE_SIZE);
134 pcie = REG_MAP(sii->wrapba[5], SI_CORE_SIZE);
136 i2s = REG_MAP(sii->wrapba[8], SI_CORE_SIZE);
235 eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
240 sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
342 if ((addrh != 0) || (sizeh != 0) || (sizel != SI_CORE_SIZE)) {
355 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
383 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
400 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
447 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
[all...]
H A Dsiutils_priv.h91 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
92 ISALIGNED((x), SI_CORE_SIZE))
93 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
H A Dsbutils.c382 ASSERT(regoff < SI_CORE_SIZE);
394 SI_CORE_SIZE);
492 sii->coresba[next] = sbba + (i * SI_CORE_SIZE);
626 sii->regs[coreidx] = REG_MAP(sbaddr, SI_CORE_SIZE);
H A Dhndpci.c781 resetctrl = (uint32 *)OSL_UNCACHED(SI_WRAP_BASE + (9 * SI_CORE_SIZE) +
H A Dsbsdram.S116 addu a0,SI_CORE_SIZE
H A Dsiutils.c115 regs = REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
492 cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/include/
H A Dhndsoc.h46 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ macro
H A Dsbconfig.h36 #define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE) /* Max cores per bus */

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