/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-cris/arch-v32/hwregs/ |
H A D | dma.h | 79 REG_WR( dma, inst, rw_cfg, e); } while( 0 ) 85 REG_WR( dma, inst, rw_cfg, r); } while( 0 ) 91 REG_WR( dma, inst, rw_cfg, s); } while( 0 ) 97 REG_WR( dma, inst, rw_cfg, c); } while( 0 ) 104 REG_WR( dma, inst, rw_stream_cmd, r ); \ 126 REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
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H A D | irq_nmi_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | strcop_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | marb_bp_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | rt_trace_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | strmux_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/cris/arch-v32/drivers/ |
H A D | iop_fw_load.c | 86 REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl); 90 REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl); 95 REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl); 147 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); 153 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0)); 174 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT()); 184 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI()); 188 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl);
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H A D | sync_serial.c | 273 REG_WR(sser, port->regi_sser, rw_cfg, cfg); 283 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); 292 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); 298 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); 444 REG_WR(dma, port->regi_dmain, rw_cfg, cfg); 445 REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); 447 REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); 448 REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); 779 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); 780 REG_WR(sse [all...] |
H A D | nandflash.c | 65 REG_WR(gio, regi_gio, rw_pa_dout, dout); 116 REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); 120 REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/cris/arch-v32/kernel/ |
H A D | time.c | 135 REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl); 151 REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl); 207 REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr); 271 REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div); 272 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */ 274 REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */ 279 REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask); 318 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
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H A D | debugport.c | 152 REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div); 153 REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div); 154 REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en); 155 REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl); 156 REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl); 182 REG_WR(ser, port->instance, rw_tr_dma_en, tr_dma_en); 203 REG_WR(ser, port->instance, rw_tr_dma_en, old); 276 REG_WR(ser, kgdb_instance, rw_ack_intr, ack_intr); 289 REG_WR (ser, kgdb_instance, rw_data_out, REG_TYPE_CONV(reg_ser_rw_data_out, int, val));
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H A D | arbiter.c | 200 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); 234 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); 286 REG_WR(marb_bp, watch->instance, rw_ack, ack); 287 REG_WR(marb, regi_marb, rw_ack_intr, ack_intr);
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H A D | dma.c | 213 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); 214 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/cris/arch-v32/boot/compressed/ |
H A D | misc.c | 156 REG_WR(ser, regi_ser, rw_dout, dout); 256 REG_WR(ser, regi_ser, rw_xoff, xoff); 276 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); 277 REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud); 278 REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); 279 REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud);
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/net/ |
H A D | bnx2.c | 240 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 250 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset); 251 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val); 263 REG_WR(bp, BNX2_CTX_CTX_DATA, val); 264 REG_WR(bp, BNX2_CTX_CTX_CTRL, 274 REG_WR(bp, BNX2_CTX_DATA_ADR, offset); 275 REG_WR(bp, BNX2_CTX_DATA, val); 290 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1); 299 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1); 328 REG_WR(b [all...] |
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-cris/arch-v32/hwregs/iop/ |
H A D | iop_version_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_crc_par_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_fifo_in_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_fifo_in_extra_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_fifo_out_extra_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_mpu_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_sap_in_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_scrc_in_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_scrc_out_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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H A D | iop_trigger_grp_defs.h | 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ macro
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