Searched refs:PMU1_PLL0_PLLCTL2 (Results 1 - 2 of 2) sorted by relevance
| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/shared/ |
| H A D | hndpmu.c | 2044 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3135 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3148 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3174 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2 + phypll_offset);
3201 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3206 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3211 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3225 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3238 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
3257 W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
[all...] |
| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/include/ |
| H A D | sbchipc.h | 1083 #define PMU1_PLL0_PLLCTL2 2 macro
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