Searched refs:PMU1_PLL0_PC2_NDIV_INT_MASK (Results 1 - 2 of 2) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/include/
H A Dsbchipc.h1092 #define PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/shared/
H A Dhndpmu.c2046 ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
2047 tmp |= ((xt->ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) & PMU1_PLL0_PC2_NDIV_INT_MASK) |
3176 tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);

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