Searched refs:DCRN_CHCR_BASE (Results 1 - 6 of 6) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-ppc/
H A Dibm405.h34 #ifdef DCRN_CHCR_BASE
35 #define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */
36 #define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */
H A Dibm403.h51 #ifdef DCRN_CHCR_BASE
52 #define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */
53 #define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dibm405gp.h85 #define DCRN_CHCR_BASE 0x0B1 macro
H A Dibm405gpr.h85 #define DCRN_CHCR_BASE 0x0B1 macro
H A Dcpci405.c76 uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
H A Dibmnp405h.h77 #define DCRN_CHCR_BASE 0x0F1 macro

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