Searched refs:CCR1 (Results 1 - 6 of 6) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-sh/cpu-sh2a/
H A Dcache.h15 #define CCR1 0xfffc1000 macro
18 /* CCR1 behaves more like the traditional CCR */
19 #define CCR CCR1
22 * Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-sh/cpu-sh2/
H A Dcache.h32 #define CCR1 0xffffffec macro
33 #define CCR CCR1
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/net/wan/
H A Ddscc4.c264 #define CCR1 0x0c macro
822 scc_writel(0x02408000, dpriv, dev, CCR1);
1337 state = scc_readl(dpriv, CCR1);
1345 scc_writel(state, dpriv, dev, CCR1);
1362 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
H A Dpc300-falc-lh.h65 /* CCR1 (Common Configuration Register 1)
1136 #define CCR1 0x09 /* Common Configuration Reg 1 */ macro
H A Dpc300_drv.c712 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
924 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/pcmcia/
H A Dsynclink_cs.c281 #define CCR1 0x2d macro
3174 /* CCR1
3185 write_reg(info, CHB + CCR1, 0x17);
3230 /* CCR1:02..00 CM[2..0] Clock Mode = 111 (clock mode 7) */
3231 val = read_reg(info, CHA + CCR1) | (BIT2 + BIT1 + BIT0);
3232 write_reg(info, CHA + CCR1, val);
3333 /* CCR1
3345 write_reg(info, CHA + CCR1, val);
3663 /* CCR1
3672 write_reg(info, CHA + CCR1,
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