Searched refs:B0TT_4 (Results 1 - 7 of 7) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf533/
H A Dmem_init.h182 #define flash_EBIU_AMBCTL0_TT B0TT_4
H A DdefBF532.h1007 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf537/
H A Dmem_init.h196 #define flash_EBIU_AMBCTL0_TT B0TT_4
H A DdefBF534.h1422 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf561/
H A Dmem_init.h188 #define flash_EBIU_AMBCTL0_TT B0TT_4
H A DdefBF561.h1439 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-bf527/
H A DdefBF52x_base.h1162 #define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */ macro

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