Searched refs:writel (Results 1 - 21 of 21) sorted by relevance

/netgear-R7800-V1.0.2.28/target/linux/lantiq/files/drivers/usb/dwc_otg/
H A Ddwc_otg_ifx.c57 #define writel ltq_w32 macro
62 writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR);
65 writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR);
67 writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR);
69 writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR);
70 writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR);
71 writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR);
76 writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_HDSEL_BIT), DANUBE_RCU_UBSCFG);
87 writel(readl(DANUBE_RCU_UBSCFG) | (1<<DANUBE_USBCFG_HOST_END_BIT), DANUBE_RCU_UBSCFG);
89 writel(read
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H A Ddwc_otg_plat.h55 #define writel ltq_w32 macro
84 writel( _value, _reg );
103 writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg );
/netgear-R7800-V1.0.2.28/package/qca-nss-drv/src/nss_hal/ipq806x/
H A Dnss_hal_pvt.c236 writel(ctl_reg0, UBI32_COREn_CLK_CTL(0));
237 writel(ctl_reg1, UBI32_COREn_CLK_CTL(1));
250 writel(ctl_reg0, UBI32_COREn_CLK_CTL(0));
251 writel(ctl_reg1, UBI32_COREn_CLK_CTL(1));
404 writel(md_reg0, UBI32_COREn_CLK_SRC0_MD(0));
405 writel(md_reg1, UBI32_COREn_CLK_SRC0_MD(1));
406 writel(ns_reg0, UBI32_COREn_CLK_SRC0_NS(0));
407 writel(ns_reg1, UBI32_COREn_CLK_SRC0_NS(1));
436 writel(0, PLL18_MODE);
442 writel(
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H A Dnss_regs.h102 writel(val, (void *)(addr + offs));
/netgear-R7800-V1.0.2.28/target/linux/s3c24xx/files-2.6.30/drivers/input/touchscreen/
H A Ds3c2410_ts.c31 * - Use ioremap and readl/writel
137 writel(S3C2410_ADCTSC_PULL_UP_DISABLE | AUTOPST,
139 writel(readl(base_addr + S3C2410_ADCCON) | S3C2410_ADCCON_ENABLE_START,
278 writel(WAIT4INT(0), base_addr+S3C2410_ADCTSC);
311 writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
319 writel(WAIT4INT(1), base_addr + S3C2410_ADCTSC);
376 writel(S3C2410_ADCCON_PRSCEN |
380 writel(0, base_addr+S3C2410_ADCCON);
384 writel(info->delay & 0xffff, base_addr + S3C2410_ADCDLY);
386 writel(WAIT4IN
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/netgear-R7800-V1.0.2.28/package/qca-nss-drv/src/
H A Dnss_pm.c347 writel(0x3, NSSTCM_CLK_SRC_CTL);
353 writel(0x2, NSSTCM_CLK_SRC_CTL);
367 writel(0x23, CE5_ACLK_SRC0_NS);
368 writel(0x23, CE5_HCLK_SRC0_NS);
369 writel(0x23, CE5_CORE_CLK_SRC0_NS);
371 writel(0x2, CE5_ACLK_SRC_CTL);
372 writel(0x2, CE5_HCLK_SRC_CTL);
373 writel(0x2, CE5_CORE_CLK_SRC_CTL);
/netgear-R7800-V1.0.2.28/target/linux/ramips/files/drivers/usb/dwc_otg/linux/
H A Ddwc_otg_plat.h80 writel( value, reg );
99 writel( (readl(reg) & ~clear_mask) | set_mask, reg );
/netgear-R7800-V1.0.2.28/package/qca-nss-drv/src/nss_hal/fsm9010/
H A Dnss_regs.h105 writel(val, (uint32_t *)(addr + offs));
/netgear-R7800-V1.0.2.28/target/linux/ubicom32/files/arch/ubicom32/include/asm/
H A Dio.h55 #define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) macro
97 static inline void writel(unsigned int val, volatile void __iomem *addr) function
132 #define __raw_writel writel
203 #define outl(x,addr) ((void) writel(x,addr))
243 #define iowrite32(val,X) writel(val,X)
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/linux_oss/
H A DmvOsSata.h103 #define MV_REG_WRITE_DWORD(base, offset, val) writel(val, base + offset)
/netgear-R7800-V1.0.2.28/target/linux/lantiq/files/drivers/usb/ifxhcd/
H A Difxusb_cif_h.c797 writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
798 writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C );
799 writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C );
800 writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C );
802 writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
809 writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
810 writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C );
811 writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C );
814 writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C);
/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/src/init/
H A Dssdk_init.c1540 writel(reg_val, hw_addr + reg_addr);
1578 writel(reg_val, psgmii_hw_addr + reg_addr);
1788 writel((value|(1<<21)), (hw_addr+0x66c+phy*0xc));
1952 writel((value&(~(1<<21))), (hw_addr+0x66c+phy*0xc));
2423 writel(0x20, gcc_addr+0xc);
2425 writel(0x0, gcc_addr+0xc);
2510 writel(0x4806, mdc_addr+0x0000);
2511 writel(0x4806, mdc_addr+0x1000);
2522 writel(0x01c6, gpio_addr+0x0000);
2523 writel(
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/netgear-R7800-V1.0.2.28/target/linux/ramips/files/drivers/usb/dwc_otg/
H A Ddwc_otg_pcd.c930 writel((uint32_t)dma_ad, &dma_desc->buf);
931 writel(sts.d32, &dma_desc->status);
945 writel((uint32_t)dma_ad, &dma_desc->buf);
946 writel(sts.d32, &dma_desc->status);
959 writel((uint32_t)dma_ad, &dma_desc->buf);
960 writel(sts.d32, &dma_desc->status);
976 writel((uint32_t)dma_ad, &dma_desc->buf);
977 writel(sts.d32, &dma_desc->status);
990 writel((uint32_t)dma_ad, &dma_desc->buf);
991 writel(st
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H A Ddwc_otg_pcd_intr.c1970 writel(sts.d32,&dma_desc->status);
1979 writel(sts.d32,&dma_desc->status);
2223 writel((uint32_t)dma_ad, &dma_desc->buf);
2224 writel(sts.d32, &dma_desc->status);
2239 writel((uint32_t)dma_ad, &dma_desc->buf);
2240 writel(sts.d32, &dma_desc->status);
2254 writel((uint32_t)dma_ad, &dma_desc->buf);
2255 writel(sts.d32, &dma_desc->status);
2272 writel((uint32_t)dma_ad, &dma_desc->buf);
2273 writel(st
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/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/
H A Dcesa_ocf_drv.c1117 writel(0, dev->reg + WINDOW_BASE(i));
1118 writel(0, dev->reg + WINDOW_CTRL(i));
1123 writel(
1129 writel(cs->base, dev->reg + WINDOW_BASE(i));
/netgear-R7800-V1.0.2.28/target/linux/ramips/files/arch/mips/pci/
H A Dpci-rt288x.c50 writel(val, rt2880_pci_base + reg);
H A Dpci-rt3883.c64 writel(val, rt3883_pci_base + reg);
/netgear-R7800-V1.0.2.28/target/linux/adm5120/files/drivers/usb/host/
H A Dadm5120.h213 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
560 writel(val, regs);
562 writel(val, regs);
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/hifn/
H A DhifnHIPP.c122 writel(val, sc->sc_bar[barno] + reg);
H A Dhifn7751.c2884 writel(val, sc->sc_bar0 + reg);
2895 writel(val, sc->sc_bar1 + reg);
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/safe/
H A Dsafe.c132 #define WRITE_REG(sc,r,val) writel((val), (sc)->sc_base_addr + (r))

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