1/*
2 **************************************************************************
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all copies.
7 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
8 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
10 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
11 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
12 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
13 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
14 **************************************************************************
15 */
16
17/**
18 * nss_regs.h
19 *	NSS register definitions.
20 */
21
22#ifndef __NSS_REGS_H
23#define __NSS_REGS_H
24
25#include <linux/types.h>
26#include <asm/io.h>
27
28#define NSS_FSM9010_TCM_SIZE SZ_64K
29#define NSS_FSM9010_TCM_BASE IOMEM(0xe4000000)
30#define NSS_FSM9010_FPB_BASE 0xfc800000
31/*
32 * CSM register offsets
33 */
34#define NSS_REGS_CORE_ID_OFFSET			0x0000
35#define NSS_REGS_RESET_CTRL_OFFSET		0x0004
36#define NSS_REGS_CORE_BAR_OFFSET		0x0008
37#define NSS_REGS_CORE_AMC_OFFSET		0x000c
38#define NSS_REGS_CORE_BOOT_ADDR_OFFSET		0x0010
39#define NSS_REGS_C2C_INTR_STATUS_OFFSET		0x0014
40#define NSS_REGS_C2C_INTR_SET_OFFSET		0x0018
41#define NSS_REGS_C2C_INTR_CLR_OFFSET		0x001c
42#define NSS_REGS_N2H_INTR_STATUS_OFFSET		0x0020
43#define NSS_REGS_N2H_INTR_SET_OFFSET		0x0024
44#define NSS_REGS_N2H_INTR_CLR_OFFSET		0x0028
45#define NSS_REGS_N2H_INTR_MASK_OFFSET		0x002c
46#define NSS_REGS_N2H_INTR_MASK_SET_OFFSET	0x0030
47#define NSS_REGS_N2H_INTR_MASK_CLR_OFFSET	0x0034
48#define NSS_REGS_CORE_INT_STAT0_TYPE_OFFSET	0x0038
49#define NSS_REGS_CORE_INT_STAT1_TYPE_OFFSET	0x003c
50#define NSS_REGS_CORE_INT_STAT2_TYPE_OFFSET	0x0040
51#define NSS_REGS_CORE_INT_STAT3_TYPE_OFFSET	0x0044
52#define NSS_REGS_CORE_IFETCH_RANGE_OFFSET	0x0048
53
54/*
55 * FPB register offsets
56 */
57#define NSS_REGS_FPB_CSR_CFG_OFFSET		0x0004
58
59/*
60 * Defines for N2H interrupts
61 *
62 * It is required to have 2 COREDUMP_COMPLETE interrupts because
63 * both NSS cores may generate interrupt simultaneously
64 */
65#define NSS_REGS_N2H_INTR_STATUS_EMPTY_BUFFER_QUEUE	(1 << 0)
66#define NSS_REGS_N2H_INTR_STATUS_DATA_COMMAND_QUEUE	(1 << 1)
67#define NSS_REGS_N2H_INTR_STATUS_DATA_QUEUE_1	    	(1 << 2)
68#define NSS_REGS_N2H_INTR_STATUS_EMPTY_BUFFERS_SOS	(1 << 10)
69#define NSS_REGS_N2H_INTR_STATUS_TX_UNBLOCKED		(1 << 11)
70#define NSS_REGS_N2H_INTR_STATUS_COREDUMP_COMPLETE_1	(1 << 13)
71#define NSS_REGS_N2H_INTR_STATUS_COREDUMP_COMPLETE_0	(1 << 14)
72
73/*
74 * Defines for H2N interrupts
75 */
76#define NSS_REGS_H2N_INTR_STATUS_EMPTY_BUFFER_QUEUE	(1 << 0)
77#define NSS_REGS_H2N_INTR_STATUS_DATA_COMMAND_QUEUE	(1 << 1)
78#define NSS_REGS_H2N_INTR_STATUS_RESET			(1 << 10)	/** Unused */
79#define NSS_REGS_H2N_INTR_STATUS_TX_UNBLOCKED		(1 << 11)
80#define NSS_REGS_H2N_INTR_STATUS_TRIGGER_COREDUMP	(1 << 15)
81
82/*
83 * clock source for NSS cores
84 */
85enum nss_regs_clk_src_select {
86	NSS_REGS_CLK_SRC_DEFAULT,
87	NSS_REGS_CLK_SRC_ALTERNATE
88};
89
90/*
91 * nss_read_32()
92 *	Read NSS register
93 */
94static inline uint32_t nss_read_32(uint32_t addr, uint32_t offs)
95{
96	return readl((uint32_t *)(addr + offs));
97}
98
99/*
100 * nss_write_32()
101 *	Write NSS register
102 */
103static inline void nss_write_32(uint32_t addr, uint32_t offs, uint32_t val)
104{
105	writel(val, (uint32_t *)(addr + offs));
106}
107
108#endif /* __NSS_REGS_H */
109