Searched refs:BIT0 (Results 1 - 22 of 22) sorted by relevance

/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/
H A DmvCtrlEnvAddrDec.h77 #define ATMWCR_WIN_DUNIT_CS0_MASK BIT0
94 #define ATMWCR_WIN_RUNIT_DEVCS0_MASK BIT0
111 #define ATMWCR_WIN_LUNIT_BYTE_SWP_MASK BIT0
H A DmvCtrlEnvAddrDec.c103 #define CTRL_DEC_WIN_EN BIT0
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/ctrlEnv/sys/
H A DmvSysPex.h102 #define PXBCR_BAR_EN BIT0
112 #define PXERBCR_EXPROM_EN BIT0
145 #define PXWCR_WIN_EN BIT0 /* Window Enable.*/
172 #define PXWRR_REMAP_EN BIT0
202 #define PXWERRR_REMAP_EN BIT0
213 #define PXBIR_IOSPACE BIT0 /* Memory Space Indicator */
245 #define PXBR_IOSPACE BIT0 /* Memory Space Indicator */
270 #define PXERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */
H A DmvCpuIfRegs.h173 #define CCSR_PCI_ACCESS_MASK BIT0
186 #define CRMR_PEX_RST_OUT_MASK BIT0
203 #define CSSRR_SYSTEM_SOFT_RST BIT0
208 #define CAMCIR_ARM_SELF_INT BIT0
218 #define CAMCIR_ARM_SELF_INT_MASK BIT0
H A DmvAhbToMbusRegs.h85 #define ATMWCR_WIN_ENABLE BIT0 /* Window Enable */
/netgear-R7800-V1.0.2.28/target/linux/amazon/files/include/asm-mips/amazon/
H A Damazon_mei.h33 #define BIT0 1<<0 macro
95 #define MEI_TO_ARC_MSGAV BIT0
106 #define ARC_TO_MEI_MSGAV BIT0
117 #define MSGAV_EN BIT0
122 #define HOST_MSTR BIT0
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci-if/
H A DmvPciIfRegs.h103 #define PSCR_IO_EN BIT0 /* IO Enable */
177 #define PBBLR_IOSPACE BIT0 /* Memory Space Indicator */
218 #define PERBAR_EXPROMEN BIT0 /* Expansion ROM Enable */
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/
H A DmvDramIf.c686 if((pBankInfo->suportedCasLatencies >> j) & BIT0 )
693 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
698 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
703 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
707 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
721 if((pBankInfo2->suportedCasLatencies >> j) & BIT0 )
728 pBankInfo2->suportedCasLatencies &= ~(BIT0 << j);
733 pBankInfo2->suportedCasLatencies &= ~(BIT0 << j);
738 pBankInfo2->suportedCasLatencies &= ~(BIT0 << j);
742 pBankInfo2->suportedCasLatencies &= ~(BIT0 <<
[all...]
H A DmvDramIfRegs.h84 #define SCSR_WIN_EN BIT0
387 #define SECR_SINGLE_BIT_ERR BIT0
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/gpp/
H A DmvGppRegs.h68 #define MV_GPP0 BIT0
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr1_2/
H A DmvDram.c194 if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4))
560 if (pDimmInfo->dimmBankDensity & BIT0)
579 if (pDimmInfo->dimmBankDensity & BIT0)
598 if (pDimmInfo->dimmBankDensity & BIT0)
859 if (dimmInfo.burstLengthSupported & BIT0)
913 if (dimmInfo.suportedCasLatencies & BIT0)
946 if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4))
962 if (dimmInfo.dimmAttributes & BIT0)
999 if (dimmInfo.dimmAttributes & BIT0)
1055 if ( spdRawData[i] & BIT0 )
[all...]
H A DmvDramIf.c432 if((pBankInfo->suportedCasLatencies >> j) & BIT0 )
439 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
444 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
449 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
453 pBankInfo->suportedCasLatencies &= ~(BIT0 << j);
477 if((pBankInfo->suportedCasLatencies >> j) & BIT0 )
479 DB(mvOsPrintf("Dram: minCasCalc choose CAS %x \n",(BIT0 << j)));
480 return (BIT0 << j);
H A DmvDramIfRegs.h78 #define SCSR_WIN_EN BIT0
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/ddr2/spd/
H A DmvSpd.c193 if (pDimmInfo->dimmTypeInfo & (BIT0 | BIT4))
555 if (pDimmInfo->dimmBankDensity & BIT0)
574 if (pDimmInfo->dimmBankDensity & BIT0)
593 if (pDimmInfo->dimmBankDensity & BIT0)
854 if (dimmInfo.burstLengthSupported & BIT0)
908 if (dimmInfo.suportedCasLatencies & BIT0)
941 if (dimmInfo.dimmTypeInfo & (BIT0 | BIT4))
957 if (dimmInfo.dimmAttributes & BIT0)
994 if (dimmInfo.dimmAttributes & BIT0)
1050 if ( spdRawData[i] & BIT0 )
[all...]
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/twsi/
H A DmvTwsiSpec.h77 #define TWSI_SLAVE_ADDR_GCE_ENA BIT0
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/
H A DmvPciRegs.h108 #define PDC_DLL_EN BIT0
112 #define PCR_MASTER_BYTE_SWAP_EN BIT0
214 #define PACBLR_EN BIT0 /* Access control window enable */
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/
H A DmvPexRegs.h129 #define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */
225 #define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/
369 #define PXSAC_IO_EN BIT0 /* IO Enable */
621 #define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/
H A DmvPex.c114 /* BIT0 - Common mode feedback */
120 regVal |= (BIT0 | BIT3);
126 regVal |= (BIT0 | BIT3);
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/kw_family/boardEnv/
H A DmvBoardEnvSpec.h203 #define RD_88F6192A_OE_HIGH (BIT0 | BIT2)
H A DmvBoardEnvLib.c841 MV_REG_BIT_SET( CPU_SYS_SOFT_RST_REG , BIT0);
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/common/
H A DmvCommon.h131 #define BIT0 0x00000001 macro
/netgear-R7800-V1.0.2.28/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/eth/gbe/
H A DmvEthDebug.c544 (macEntry & BIT0) ? "Accept" : "Reject", (macEntry >> 1) & 0x7);

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