Searched refs:vclk (Results 1 - 12 of 12) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dclock2xxx.c32 struct clk *vclk, *sclk, *dclk; variable in typeref:struct:clk
45 if (vclk == NULL || sclk == NULL)
49 clk_set_rate(vclk, rate);
H A Dclock.h135 extern struct clk *vclk, *sclk;
H A Dclock2420_data.c1900 vclk = clk_get(NULL, "virt_prcm_set");
H A Dclock2430_data.c1989 vclk = clk_get(NULL, "virt_prcm_set");
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/via/
H A Dchip.h170 u32 vclk; /*panel mode clock value */ member in struct:lvds_setting_information
H A Dvt1636.c253 index = get_clk_range_index(plvds_setting_info->vclk);
275 index = get_clk_range_index(plvds_setting_info->vclk);
297 index = get_clk_range_index(plvds_setting_info->vclk);
H A Dlcd.c620 plvds_setting_info->vclk = panel_crt_table->clk;
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/aty/
H A Daty128fb.c390 u32 vclk; member in struct:aty128_pll
1324 u32 vclk; /* in .01 MHz */ local
1328 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1331 if (vclk > c.ppll_max)
1332 vclk = c.ppll_max;
1333 if (vclk * 12 < c.ppll_min)
1334 vclk = c.ppll_min/12;
1338 output_freq = post_dividers[i] * vclk;
1353 pll->vclk = vclk;
[all...]
H A Dradeon_base.c462 unsigned long long hz, vclk; local
506 vclk = (long long)hTotal * (long long)vTotal * hz;
558 vclk *= denom;
559 do_div(vclk, 1000 * num);
560 xtal = vclk;
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/gpu/drm/nouveau/
H A Dnouveau_calc.c250 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) argument
255 nv04_update_arb(dev, vclk, bpp, burst, lwm);
H A Dnouveau_hw.h56 extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/
H A Dtridentfb.c1016 unsigned long vclk; local
1175 vclk = PICOS2KHZ(info->var.pixclock);
1181 vclk *= 2;
1183 set_vclk(par, vclk);

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